On Tue, Dec 13, 2011 at 03:08:53PM +0000, Simon Farnsworth wrote:
> Evergreen and later Radeons let the driver choose a macro tile layout,
> within certain constraints. If we don't set the appropriate fields
> correctly, the card will use a layout that doesn't normally meet the
> constraints on Evergreen tiling.
>
> For now, select 8x8 aspect 1 macrotiles, as this makes it possible to
> guarantee that we meet the hardware constraints. Once macrotiling is
> reliable, we can consider a better API to let us exploit the hardware
> capabilities.
>
> Signed-off-by: Simon Farnsworth <simon.farnsworth at onelan.co.uk>
NAK
We don't want to enforce those value in kernel. I am working on fixing
tiling accross the stack and such patch would only hurt us in the
future.
Cheers,
Jerome
> ---
>
> This doesn't fix my problems with enabling macro tiling, but it does help
> somewhat. I also need to fix alignment in the DDX and Mesa to avoid
> misrendering, at which point I see CP lockups instead.
>
> I'm therefore sending this, the DDX patch, and the Mesa patch out in order
> to avoid getting stuck in a world where I have an 80% fix, someone else has
> an 80% fix, and if only we talked, we'd have a 100% fix.
>
> drivers/gpu/drm/radeon/atombios_crtc.c | 4 ++++
> drivers/gpu/drm/radeon/evergreen_cs.c | 9 +++++++++
> drivers/gpu/drm/radeon/evergreend.h | 7 +++++++
> 3 files changed, 20 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
> b/drivers/gpu/drm/radeon/atombios_crtc.c
> index 2b97262..f982975 100644
> --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> @@ -1113,6 +1113,10 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
> else
> tmp = rdev->config.evergreen.tile_config;
>
> + fb_format |=
> (EVERGREEN_GRPH_BANK_HEIGHT(EVERGREEN_ADDR_SURF_BANK_HEIGHT_8) |
> +
> EVERGREEN_GRPH_BANK_WIDTH(EVERGREEN_ADDR_SURF_BANK_WIDTH_8) |
> +
> EVERGREEN_GRPH_MACRO_TILE_ASPECT(EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1));
> +
> switch ((tmp & 0xf0) >> 4) {
> case 0: /* 4 banks */
> fb_format |=
> EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
> diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c
> b/drivers/gpu/drm/radeon/evergreen_cs.c
> index b53d1c6..a14a04e 100644
> --- a/drivers/gpu/drm/radeon/evergreen_cs.c
> +++ b/drivers/gpu/drm/radeon/evergreen_cs.c
> @@ -532,6 +532,9 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser
> *p, u32 reg, u32 idx)
> ib[idx] |=
> Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
> track->db_z_info |=
> Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
> if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
> + ib[idx] |=
> (DB_BANK_WIDTH(ADDR_SURF_BANK_WIDTH_8) |
> +
> DB_BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> +
> DB_MACRO_TILE_ASPECT(ADDR_SURF_MACRO_TILE_ASPECT_1));
> ib[idx] |=
> DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
> ib[idx] |=
> DB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
> }
> @@ -736,6 +739,9 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser
> *p, u32 reg, u32 idx)
> return -EINVAL;
> }
> if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
> + ib[idx] |= (CB_BANK_WIDTH(ADDR_SURF_BANK_WIDTH_8) |
> + CB_BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> +
> CB_MACRO_TILE_ASPECT(ADDR_SURF_MACRO_TILE_ASPECT_1));
> ib[idx] |=
> CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
> ib[idx] |=
> CB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
> }
> @@ -1360,6 +1366,9 @@ static int evergreen_packet3_check(struct
> radeon_cs_parser *p,
> if (reloc->lobj.tiling_flags &
> RADEON_TILING_MACRO) {
> ib[idx+1+(i*8)+6] |=
> TEX_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
> ib[idx+1+(i*8)+7] |=
> TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
> + ib[idx+1+(i*8)+8] |=
> (TEX_BANK_WIDTH(ADDR_SURF_BANK_WIDTH_8) |
> +
> TEX_BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> +
> TEX_MACRO_TILE_ASPECT(ADDR_SURF_MACRO_TILE_ASPECT_1));
> }
> }
> texture = reloc->robj;
> diff --git a/drivers/gpu/drm/radeon/evergreend.h
> b/drivers/gpu/drm/radeon/evergreend.h
> index e00039e..3731e8f 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -903,6 +903,7 @@
> # define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
> # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
> # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
> +# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
> #define DB_STENCIL_INFO 0x28044
> #define DB_Z_READ_BASE 0x28048
> #define DB_STENCIL_READ_BASE 0x2804c
> @@ -978,6 +979,11 @@
> # define ADDR_SURF_BANK_HEIGHT_2 1
> # define ADDR_SURF_BANK_HEIGHT_4 2
> # define ADDR_SURF_BANK_HEIGHT_8 3
> +# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
> +# define ADDR_SURF_MACRO_TILE_ASPECT_1 0
> +# define ADDR_SURF_MACRO_TILE_ASPECT_2 1
> +# define ADDR_SURF_MACRO_TILE_ASPECT_4 2
> +# define ADDR_SURF_MACRO_TILE_ASPECT_8 3
> #define CB_COLOR0_DIM 0x28c78
> /* only CB0-7 blocks have these regs */
> #define CB_COLOR0_CMASK 0x28c7c
> @@ -1166,6 +1172,7 @@
> #define SQ_TEX_RESOURCE_WORD6_0 0x30018
> # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
> #define SQ_TEX_RESOURCE_WORD7_0 0x3001c
> +# define TEX_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
> # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
> # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
> # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
> --
> 1.7.6.4
>
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