From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> Hi All,
This patch series adds DU/DSI clocks and provides support for the MIPI DSI interface on the RZ/V2H(P) SoC. It was originally part of series [0], but has now been split into 6 patches due to dependencies on the clock driver, making it easier to review and merge. [0] https://lore.kernel.org/all/20250430204112.342123-1-prabhakar.mahadev-lad...@bp.renesas.com/ v6->v7: - Renamed pllclk to pllrefclk in DT binding - Added a new patch to add instance field to struct pll - Renamed rzv2h_pll_div_limits to rzv2h_pll_limits - Included fout_min and fout_max in the rzv2h_pll_limits structure - Renamed rzv2h_plldsi_parameters to rzv2h_pll_div_pars and re-structured for readability - Dropped rzv2h_dsi_get_pll_parameters_values() instead added modular apis to calculate the PLL parameters ie rzv2h_get_pll_pars/rzv2h_get_pll_div_pars/ rzv2h_get_pll_dtable_pars - Dropped plldsi_limits from rzv2h_cpg_info structure - Updated the DSI driver to use the new PLL APIs - Included the LPCLK patch - Rebased the changes on next-20250728 v5-> v6: - Renamed CPG_PLL_STBY_SSCGEN_WEN to CPG_PLL_STBY_SSC_EN_WEN - Updated CPG_PLL_CLK1_DIV_K, CPG_PLL_CLK1_DIV_M, and CPG_PLL_CLK1_DIV_P macros to use GENMASK - Updated req->rate in rzv2h_cpg_plldsi_div_determine_rate() - Dropped the cast in rzv2h_cpg_plldsi_div_set_rate() - Dropped rzv2h_cpg_plldsi_round_rate() and implemented rzv2h_cpg_plldsi_determine_rate() instead - Made use of FIELD_PREP() - Moved CPG_CSDIV1 macro in patch 2/4 - Dropped two_pow_s in rzv2h_dsi_get_pll_parameters_values() - Used mul_u32_u32() while calculating output_m and output_k_range - Used div_s64() instead of div64_s64() while calculating pll_k - Used mul_u32_u32() while calculating fvco and fvco checks - Rounded the final output using DIV_U64_ROUND_CLOSEST() - Renamed CLK_DIV_PLLETH_LPCLK to CLK_CDIV4_PLLETH_LPCLK - Renamed CLK_CSDIV_PLLETH_LPCLK to CLK_PLLETH_LPCLK_GEAR - Renamed CLK_PLLDSI_SDIV2 to CLK_PLLDSI_GEAR - Renamed plldsi_sdiv2 to plldsi_gear - Preserved the sort order (by part number). - Added reviewed tag from Geert. - Made use of GENMASK() macro for PLLCLKSET0R_PLL_*, PHYTCLKSETR_* and PHYTHSSETR_* macros. - Replaced 10000000UL with 10 * MEGA - Renamed mode_freq_hz to mode_freq_khz in rzv2h_dsi_mode_calc - Replaced `i -= 1;` with `i--;` - Renamed RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA to RZV2H_MIPI_DPHY_FOUT_MIN_IN_MHZ and RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA to RZV2H_MIPI_DPHY_FOUT_MAX_IN_MHZ. Cheers, Prabhakar Lad Prabhakar (6): clk: renesas: rzv2h-cpg: Add instance field to struct pll clk: renesas: rzv2h-cpg: Add support for DSI clocks clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N drm: renesas: rz-du: mipi_dsi: Add support for LPCLK clock handling drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC .../bindings/display/bridge/renesas,dsi.yaml | 120 ++++-- drivers/clk/renesas/r9a09g057-cpg.c | 62 +++ drivers/clk/renesas/rzv2h-cpg.c | 309 +++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 29 +- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 350 ++++++++++++++++ .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 34 ++ include/linux/clk/renesas-rzv2h-cpg-pll.h | 395 ++++++++++++++++++ 7 files changed, 1257 insertions(+), 42 deletions(-) create mode 100644 include/linux/clk/renesas-rzv2h-cpg-pll.h -- 2.50.1
