On 7/29/2025 7:36 PM, neil.armstr...@linaro.org wrote:
> On 20/07/2025 14:16, Akhil P Oommen wrote:
>> Add the IFPC restore register list and enable IFPC support on Adreno
>> X1-85 gpu.
>>
>> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 +++++++++++++++++++++
>> +++++++++-
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
>> 3 files changed, 78 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/
>> drm/msm/adreno/a6xx_catalog.c
>> index
>> 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981
>> 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[]
>> = {
>>
>
> <snip>
>
>> +
>> static const struct adreno_info a7xx_gpus[] = {
>> {
>> .chip_ids = ADRENO_CHIP_IDS(0x07000200),
>> @@ -1432,12 +1495,13 @@ static const struct adreno_info a7xx_gpus[] = {
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> ADRENO_QUIRK_HAS_HW_APRIV |
>> - ADRENO_QUIRK_PREEMPTION,
>> + ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC,
>> .init = a6xx_gpu_init,
>> .a6xx = &(const struct a6xx_info) {
>> .hwcg = a740_hwcg,
>> .protect = &a730_protect,
>> .pwrup_reglist = &a7xx_pwrup_reglist,
>> + .ifpc_reglist = &a750_ifpc_reglist,
>> .gmu_chipid = 0x7050001,
>> .gmu_cgc_mode = 0x00020202,
>> },
>> @@ -1459,6 +1523,7 @@ static const struct adreno_info a7xx_gpus[] = {
>> .a6xx = &(const struct a6xx_info) {
>> .protect = &a730_protect,
>> .pwrup_reglist = &a7xx_pwrup_reglist,
>> + .ifpc_reglist = &a750_ifpc_reglist,
>
> So far it's stable on a750 so I think can safely add ADRENO_QUIRK_IFPC
> here aswell.
Thanks for testing. I will enable it for a750 in the next revision.
-Akhil
>
> Neil
>
> <snip>
>
