The FLD_MOD function takes the start and end bits as parameter and will
generate a mask out of them, twice.
Let's pass the mask, so the caller can generate it once and we would use
it twice.
Signed-off-by: Maxime Ripard <mrip...@kernel.org>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c
b/drivers/gpu/drm/tidss/tidss_dispc.c
index
30f281221a5de6b69cc3edd2bf643cf0f8bea63b..e4729a5b79ed5d554e05c020adb7e2d3e7a8f4d3
100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -607,26 +607,25 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32
hw_videoport)
/*
* TRM gives bitfields as start:end, where start is the higher bit
* number. For example 7:0
*/
-static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end)
+static u32 FLD_MOD(u32 orig, u32 val, u32 mask)
{
- return (orig & ~GENMASK(start, end)) | FIELD_PREP(GENMASK(start, end),
- val);
+ return (orig & ~mask) | FIELD_PREP(mask, val);
}
static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end)
{
return FIELD_GET(GENMASK(start, end), dispc_read(dispc, idx));
}
static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val,
u32 start, u32 end)
{
- dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val,
- start, end));
+ dispc_write(dispc, idx,
+ FLD_MOD(dispc_read(dispc, idx), val, GENMASK(start, end)));
}
static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,
u32 start, u32 end)
{
@@ -636,12 +635,11 @@ static u32 VID_REG_GET(struct dispc_device *dispc, u32
hw_plane, u32 idx,
static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,
u32 val, u32 start, u32 end)
{
dispc_vid_write(dispc, hw_plane, idx,
- FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),
- val, start, end));
+ FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), val,
GENMASK(start, end)));
}
static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx,
u32 start, u32 end)
{
@@ -649,20 +647,19 @@ static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp,
u32 idx,
}
static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32
val,
u32 start, u32 end)
{
- dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx),
- val, start, end));
+ dispc_vp_write(dispc, vp, idx,
+ FLD_MOD(dispc_vp_read(dispc, vp, idx), val,
GENMASK(start, end)));
}
static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx,
u32 val, u32 start, u32 end)
{
dispc_ovr_write(dispc, ovr, idx,
- FLD_MOD(dispc_ovr_read(dispc, ovr, idx),
- val, start, end));
+ FLD_MOD(dispc_ovr_read(dispc, ovr, idx), val,
GENMASK(start, end)));
}
static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport)
{
dispc_irq_t vp_stat = 0;
@@ -1155,11 +1152,12 @@ static void dispc_enable_am65x_oldi(struct dispc_device
*dispc, u32 hw_videoport
dev_warn(dispc->dev, "%s: %d port width not supported\n",
__func__, fmt->data_width);
oldi_cfg |= BIT(7); /* DEPOL */
- oldi_cfg = FLD_MOD(oldi_cfg, fmt->am65x_oldi_mode_reg_val, 3, 1);
+ oldi_cfg = FLD_MOD(oldi_cfg, fmt->am65x_oldi_mode_reg_val,
+ GENMASK(3, 1));
oldi_cfg |= BIT(12); /* SOFTRST */
oldi_cfg |= BIT(0); /* ENABLE */
--
2.50.1
