On Wed, Jul 30, 2025 at 02:45:13PM +0200, Konrad Dybcio wrote: > On 7/30/25 2:39 PM, Ayushi Makhija wrote: > > Currently, the high bitfield of certain DSI registers > > do not align with the configuration of the SWI registers > > description. This can lead to wrong programming these DSI > > registers, for example for 4k resloution where H_TOTAL is > > taking 13 bits but software is programming only 12 bits > > because of the incorrect bitmask for H_TOTAL bitfeild, > > this is causing DSI FIFO errors. To resolve this issue, > > increase the high bitfield of the DSI registers from 12 bits > > to 16 bits in dsi.xml to match the SWI register configuration. > > > > Signed-off-by: Ayushi Makhija <quic_amakh...@quicinc.com> > > --- > > drivers/gpu/drm/msm/registers/display/dsi.xml | 28 +++++++++---------- > > 1 file changed, 14 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml > > b/drivers/gpu/drm/msm/registers/display/dsi.xml > > index 501ffc585a9f..c7a7b633d747 100644 > > --- a/drivers/gpu/drm/msm/registers/display/dsi.xml > > +++ b/drivers/gpu/drm/msm/registers/display/dsi.xml > > @@ -159,28 +159,28 @@ > > xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> > > <bitfield name="RGB_SWAP" low="12" high="14" > > type="dsi_rgb_swap"/> > > </reg32> > > <reg32 offset="0x00020" name="ACTIVE_H"> > > - <bitfield name="START" low="0" high="11" type="uint"/> > > - <bitfield name="END" low="16" high="27" type="uint"/> > > + <bitfield name="START" low="0" high="15" type="uint"/> > > + <bitfield name="END" low="16" high="31" type="uint"/> > > </reg32> > > <reg32 offset="0x00024" name="ACTIVE_V"> > > - <bitfield name="START" low="0" high="11" type="uint"/> > > - <bitfield name="END" low="16" high="27" type="uint"/> > > + <bitfield name="START" low="0" high="15" type="uint"/> > > + <bitfield name="END" low="16" high="31" type="uint"/> > > </reg32> > > <reg32 offset="0x00028" name="TOTAL"> > > - <bitfield name="H_TOTAL" low="0" high="11" type="uint"/> > > - <bitfield name="V_TOTAL" low="16" high="27" type="uint"/> > > + <bitfield name="H_TOTAL" low="0" high="15" type="uint"/> > > + <bitfield name="V_TOTAL" low="16" high="31" type="uint"/> > > </reg32> > > <reg32 offset="0x0002c" name="ACTIVE_HSYNC"> > > - <bitfield name="START" low="0" high="11" type="uint"/> > > - <bitfield name="END" low="16" high="27" type="uint"/> > > + <bitfield name="START" low="0" high="15" type="uint"/> > > + <bitfield name="END" low="16" high="31" type="uint"/> > > </reg32> > > <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS"> > > - <bitfield name="START" low="0" high="11" type="uint"/> > > - <bitfield name="END" low="16" high="27" type="uint"/> > > + <bitfield name="START" low="0" high="15" type="uint"/> > > + <bitfield name="END" low="16" high="31" type="uint"/> > > </reg32> > > <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS"> > > FWIW looks like at least on 8280, ACTIVE_VSYNC_HPOS offset = 0x38 > and HPOS doesn't exist
All registers here are shifted by 0x4 for historical and practical reasons. -- With best wishes Dmitry
