The REG_FLD_MOD function takes the start and end bits as parameter and
will generate a mask out of them.
This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.
Let's change REG_FLD_MOD to take the mask as an argument instead, and
let the caller create the mask. Eventually, this mask will be moved to a
define.
Signed-off-by: Maxime Ripard <mrip...@kernel.org>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c
b/drivers/gpu/drm/tidss/tidss_dispc.c
index
807ab0e0afc7f95efe55764dcb08da695fb85963..1b2791e8c04c463552ad370f48dce8eae5b94702
100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -610,16 +610,16 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32
hw_videoport)
*/
#define REG_GET(dispc, idx, mask) \
((u32)FIELD_GET((mask), dispc_read((dispc), (idx))))
-#define REG_FLD_MOD(dispc, idx, val, start, end) \
+#define REG_FLD_MOD(dispc, idx, val, mask) \
({ \
struct dispc_device *_dispc = (dispc); \
u32 _idx = (idx); \
u32 _reg = dispc_read(_dispc, _idx); \
- FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \
+ FIELD_MODIFY((mask), &_reg, (val)); \
dispc_write(_dispc, _idx, _reg); \
})
#define VID_REG_GET(dispc, hw_plane, idx, start, end) \
((u32)FIELD_GET(GENMASK((start), (end)), \
@@ -2331,13 +2331,13 @@ static void dispc_k2g_plane_init(struct dispc_device
*dispc)
unsigned int hw_plane;
dev_dbg(dispc->dev, "%s()\n", __func__);
/* MFLAG_CTRL = ENABLED */
- REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
+ REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0));
/* MFLAG_START = MFLAGNORMALSTARTMODE */
- REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
+ REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6));
for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
u32 thr_low, thr_high;
u32 mflag_low, mflag_high;
@@ -2382,17 +2382,17 @@ static void dispc_k3_plane_init(struct dispc_device
*dispc)
u32 cba_lo_pri = 1;
u32 cba_hi_pri = 0;
dev_dbg(dispc->dev, "%s()\n", __func__);
- REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0);
- REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3);
+ REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0));
+ REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3));
/* MFLAG_CTRL = ENABLED */
- REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
+ REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0));
/* MFLAG_START = MFLAGNORMALSTARTMODE */
- REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
+ REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6));
for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
u32 thr_low, thr_high;
u32 mflag_low, mflag_high;
@@ -2916,11 +2916,11 @@ static int dispc_softreset(struct dispc_device *dispc)
dispc_softreset_k2g(dispc);
return 0;
}
/* Soft reset */
- REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
+ REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1));
/* Wait for reset to complete */
ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
val, val & 1, 100, 5000);
if (ret) {
dev_err(dispc->dev, "failed to reset dispc\n");
--
2.50.1
