On 2025-08-30 at 09:55 +1000, John Hubbard <jhubb...@nvidia.com> wrote...
> On 8/27/25 1:19 AM, Alistair Popple wrote:
> > Set the correct DMA mask. Without this DMA will fail on some setups.
> >
> > Signed-off-by: Alistair Popple <apop...@nvidia.com>
> > ---
> > drivers/gpu/nova-core/driver.rs | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/nova-core/driver.rs
> > b/drivers/gpu/nova-core/driver.rs
> > index 274989ea1fb4a..3e154ffb6be4b 100644
> > --- a/drivers/gpu/nova-core/driver.rs
> > +++ b/drivers/gpu/nova-core/driver.rs
> > @@ -1,6 +1,9 @@
> > // SPDX-License-Identifier: GPL-2.0
> >
> > -use kernel::{auxiliary, bindings, c_str, device::Core, pci, prelude::*,
> > sizes::SZ_16M, sync::Arc};
> > +use kernel::{
> > + auxiliary, bindings, c_str, device::Core, dma::Device, dma::DmaMask,
> > pci, prelude::*,
> > + sizes::SZ_16M, sync::Arc,
> > +};
> >
> > use crate::gpu::Gpu;
> >
> > @@ -34,6 +37,9 @@ fn probe(pdev: &pci::Device<Core>, _info: &Self::IdInfo)
> > -> Result<Pin<KBox<Self
> > pdev.enable_device_mem()?;
> > pdev.set_master();
> >
> > + // SAFETY: No DMA allocations have been made yet
> > + unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<48>())? };
>
> Eventually, should be 52 bits wide, rather than 48. Or so I believe from
> looking at various drivers, including Nouveau (which uses 52-bit for
> Blackwell) and mlx* (which use a 64-bit mask).
>
> However, it works for the current series, because this series only supports
> Ampere GPUs, and 48 bits suffices for those.
Actually based on both Nouveau and our internal docs this should be 47-bits. I
suspect I just chose 48 during initial bring-up because that's what most CPUs
support but neglected to add the TODO to actually go and check this. So will fix
for v2.
> So, you could leave this patch as-is, and I'll change 48 --> 52 in the
> upcoming Hopper/Blackwell series. Or you can change it now.
We can't of course just change this to 52 bits because this needs to reflect
what the GPU HW supports. So ideally this needs to come from the HAL. I left
this hard-coded because in the short-term leaving it as 47 bits even for
Blackwell won't cause any issues. It may force usage of an IOMMU to address
physical addresses greater than 47-bits when it otherwise wouldn't for
Hopper/Blackwell (it would always have to for Ampere/Turing), but short-term I
doubt many systems actually have physical memory above 47-bits anyway.
In other words you could leave this as 47 bits in the upcoming Hopper/Blackwell
series or use the HAL we have come up with (if that is available) to obtain the
optimal value.
> Either way is fine, so:
>
>
> Reviewed-by: John Hubbard <jhubb...@nvidia.com>
Thanks.
> thanks,
> --
> John Hubbard
>
> > +
> > let bar = Arc::pin_init(
> > pdev.iomap_region_sized::<BAR0_SIZE>(0,
> > c_str!("nova-core/bar0")),
> > GFP_KERNEL,
>
>
