On 9/8/2025 9:52 PM, Konrad Dybcio wrote: > On 8/18/25 9:17 AM, Akhil P Oommen wrote: >> On 8/16/2025 3:45 AM, Dmitry Baryshkov wrote: >>> On Thu, Aug 14, 2025 at 07:52:13PM +0200, Konrad Dybcio wrote: >>>> On 8/14/25 6:38 PM, Akhil P Oommen wrote: >>>>> On 8/14/2025 7:56 PM, Neil Armstrong wrote: >>>>>> Hi, >>>>>> >>>>>> On 14/08/2025 13:22, Konrad Dybcio wrote: >>>>>>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>>>>>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>>>>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>>>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>>>>>>> along >>>>>>>>>> the Frequency and Power Domain level, but by default we leave the >>>>>>>>>> OPP core scale the interconnect ddr path. >>>>>>>>>> >>>>>>>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>>>>>>> parameters >>>>>>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>>>>>>> >>>>>>>>>> Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com> >>>>>>>>>> Signed-off-by: Neil Armstrong <neil.armstr...@linaro.org> >>>>>>>>>> --- >>>>>>>>>> Changes in v2: >>>>>>>>>> - Used proper ACV perfmode bit/freq >>>>>>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>>>>>>> gpu-bwvote-v1-1-946619b0f...@linaro.org >>>>>>>>>> --- >>>>>>>>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>>>>>>> 1 file changed, 11 insertions(+) >>>>>>>>>> >>>>>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>>>>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>>> index >>>>>>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 >>>>>>>>>> 100644 >>>>>>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = >>>>>>>>>> { >>>>>>>>>> .pwrup_reglist = &a7xx_pwrup_reglist, >>>>>>>>>> .gmu_chipid = 0x7050001, >>>>>>>>>> .gmu_cgc_mode = 0x00020202, >>>>>>>>>> + .bcms = (const struct a6xx_bcm[]) { >>>>>>>>>> + { .name = "SH0", .buswidth = 16 }, >>>>>>>>>> + { .name = "MC0", .buswidth = 4 }, >>>>>>>>>> + { >>>>>>>>>> + .name = "ACV", >>>>>>>>>> + .fixed = true, >>>>>>>>>> + .perfmode = BIT(3), >>>>>>>>>> + .perfmode_bw = 16500000, >>>>>>>>> >>>>>>>>> Reviewed-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com> >>>>>>>> >>>>>>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) >>>>> >>>>> You are right that BIT(2) is GPU specific, but that support was >>>>> commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets >>>>> use that in Linux too. >>>>> >>>>> I know some docs show BIT(2) support, but lets not bring in untested >>>>> configurations. >>>> >>>> Eh, then let's get the docs fixed if you don't trust them because we can't >>>> work like that.. >>>> >>>> FWIW this is information from per-platform RPMh cmd-db data >>> >>> If it comes from cmd-db, then we should be requesting it from the cmd-db >>> driver rather than hardcoding it here. > > No, what I meant is that there is a piece of configuration that reflects > what goes into cmd-db as its compiled and that's where I found that > information > >> >> Not really. This should be under the control of GPU driver. >> BIT(3) is correct for X1E. > > BIT(3) is for APPS, see the interconnect driver which also uses it. > This will create conflicts and may cause unvotes when some other > driver requests perf_mode through the ICC API, but the GPU is sitting > idle.
No. GPU vote goes via a different DRV. So it is independent. Anyway, I checked this further earlier. X1E platform doesn't implement any perfmode vote. So both BIT(3) and BIT(2) are no-op and are ignored by AOSS. ICC driver's vote too should be no-op on X1E. -Akhil. > > Konrad
