Hi Chris Brandt, Thanks for the patch.
> -----Original Message----- > From: Chris Brandt <chris.bra...@renesas.com> > Sent: 12 September 2025 15:21 > Subject: [PATCH v2 0/2] Remove hard coded values for MIPI-DSI > > When the initial drivers were submitted, some of the timing was hard coded > and did not allow for any > MIPI-DSI panel to be attached. > In general, panels or bridges can only be supported if MIPI-DSI lanes were 4. > If the number of lanes were 3,2,1, the math no longer works out. > > A new API was created for the clock driver because the behaivior of the clock > driver depends on DPI vs > MIPI, the screen resolution, and the number of MIPI lanes. > > > Testing: > * RZ/G2L SMARC (MIPI-DSI to HDMI bridge, lanes = 4) > * RZ/G2L-SBC (MIPI-DSI to LCD panel, lanes = 2) > * RZ/G2UL SMARC (DPI to HDMI bridge) > > > Regression Testing: > There are 2 patches in this series. > If you just apply the first patch that only modifies the clock driver, the > operation of the RZ/G2L > SMARC and RZ/G2UL SMARC remains the same. > > However of course, the second patch is needed in the mipi-dsi driver in order > to make sure of the new > API so that lanes 3,2,1 can be supported. Reviewed-by: Biju Das <biju.das...@bp.renesas.com> Tested-by: Biju Das <biju.das...@bp.renesas.com> Cheers, Biju > > > > Chris Brandt (2): > clk: renesas: rzg2l: Remove DSI clock rate restrictions > drm: renesas: rz-du: Set DSI divider based on target MIPI device > > drivers/clk/renesas/rzg2l-cpg.c | 129 ++++++++++++++++-- > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 18 +++ > include/linux/clk/renesas.h | 4 + > 3 files changed, 141 insertions(+), 10 deletions(-) > > -- > 2.50.1
