[PATCH v1 1/2] gpu/drm: tegra: dsi: make SOL delay calculation mode independent

[Svyatoslav Ryhel]

Move SOL delay calculation outside of video mode conditions.

Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com>
---
 drivers/gpu/drm/tegra/dsi.c | 41 +++++++++++++++----------------------
 1 file changed, 17 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 924611061cfa..aab555a2eb68 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -560,11 +560,6 @@ static void tegra_dsi_configure(struct tegra_dsi *dsi, 
unsigned int pipe,
                tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
                tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
                tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
-
-               /* set SOL delay (for non-burst mode only) */
-               tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
-
-               /* TODO: implement ganged mode */
        } else {
                u16 bytes;
 
@@ -586,28 +581,26 @@ static void tegra_dsi_configure(struct tegra_dsi *dsi, 
unsigned int pipe,
                value = MIPI_DCS_WRITE_MEMORY_START << 8 |
                        MIPI_DCS_WRITE_MEMORY_CONTINUE;
                tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
+       }
 
-               /* set SOL delay */
-               if (dsi->master || dsi->slave) {
-                       unsigned long delay, bclk, bclk_ganged;
-                       unsigned int lanes = state->lanes;
-
-                       /* SOL to valid, valid to FIFO and FIFO write delay */
-                       delay = 4 + 4 + 2;
-                       delay = DIV_ROUND_UP(delay * mul, div * lanes);
-                       /* FIFO read delay */
-                       delay = delay + 6;
-
-                       bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
-                       bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
-                       value = bclk - bclk_ganged + delay + 20;
-               } else {
-                       /* TODO: revisit for non-ganged mode */
-                       value = 8 * mul / div;
-               }
+       /* set SOL delay */
+       if (dsi->master || dsi->slave) {
+               unsigned long delay, bclk, bclk_ganged;
+               unsigned int lanes = state->lanes;
 
-               tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
+               /* SOL to valid, valid to FIFO and FIFO write delay */
+               delay = 4 + 4 + 2;
+               delay = DIV_ROUND_UP(delay * mul, div * lanes);
+               /* FIFO read delay */
+               delay = delay + 6;
+
+               bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
+               bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
+               value = bclk - bclk_ganged + delay + 20;
+       } else {
+               value = 8 * mul / div;
        }
+       tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
 
        if (dsi->slave) {
                tegra_dsi_configure(dsi->slave, pipe, mode);
-- 
2.48.1