> > > > Verisilicon has a series of display controllers prefixed with DC > > > > and > > > > with self-identification facility like their GC series GPUs. > > > > > > > > Add a device tree binding for it. > > > > > > > > Depends on the specific DC model, it can have either one or two > > > > display > > > > outputs, and each display output could be set to DPI signal or > > > > "DP" > > > > signal (which seems to be some plain parallel bus to HDMI > > > > controllers). > > > > > > > > Signed-off-by: Icenowy Zheng <u...@icenowy.me> > > > > --- > > > > Changes in v2: > > > > - Fixed misspelt "versilicon" in title. > > > > - Moved minItems in clock properties to be earlier than items. > > > > - Re-aligned multi-line clocks and resets in example. > > > > > > > > .../bindings/display/verisilicon,dc.yaml | 127 > > > > ++++++++++++++++++ > > > > 1 file changed, 127 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > > b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > > new file mode 100644 > > > > index 0000000000000..07fedc4c7cc13 > > > > --- /dev/null > > > > +++ > > > > b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > > @@ -0,0 +1,127 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Verisilicon DC-series display controllers > > > > + > > > > +maintainers: > > > > + - Icenowy Zheng <u...@icenowy.me> > > > > + > > > > +properties: > > > > + $nodename: > > > > + pattern: "^display@[0-9a-f]+$" > > > > + > > > > + compatible: > > > > + const: verisilicon,dc > > > > > > This needs an SoC specific compatible. Generally licensed IP > > > compatibles > > > are useless because the specs aren't public and there's always > > > integration quirks. > > > > This mimics the GPU IPs by the same vendor, see gpu/vivante,gc.yaml , > > which contain the exact same set of identification registers > > (including > > a "customer id" one that can differienate the same configured IP on > > StarFive JH7110 and T-Head TH1520). > > > > If we can get vivante,gc to work w/o SoC specific compatible, then we > > should be able to get verisilicon,dc to work too. > > Well maybe I should add etnaviv people to the recipient list, to allow > them to tell us the magic behind vivante,gc . >
Vivante GPUs are special because they contain registers that allow them to be fully identified - see etnaviv_hw_identify(..). We can read out the following information: - model - revision - product_id - customer_id - eco_id This information, in combination with a hardware database (hwdb) in kernel/userspace, is enough to support these GPUs/NPUs across different SoC vendors. -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy
