Hi Geert, Thank you for the review.
On Wed, Sep 24, 2025 at 2:05 PM Geert Uytterhoeven <[email protected]> wrote: > > Hi Prabhakar, > > On Wed, 3 Sept 2025 at 18:17, Prabhakar <[email protected]> wrote: > > From: Lad Prabhakar <[email protected]> > > > > Add support for PLLDSI and PLLDSI divider clocks. > > > > Introduce the `renesas-rzv2h-cpg-pll.h` header to centralize and share > > PLLDSI related data structures, limits, and algorithms between the > > RZ/V2H(P) CPG and DSI drivers. > > > > The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly > > different parameter limits and omits the programmable divider present in > > CPG. To ensure precise frequency calculations, especially for milliHz-level > > accuracy needed by the DSI driver, the shared algorithm allows both drivers > > to compute PLL parameters consistently using the same logic and input > > clock. > > > > Co-developed-by: Fabrizio Castro <[email protected]> > > Signed-off-by: Fabrizio Castro <[email protected]> > > Signed-off-by: Lad Prabhakar <[email protected]> > > Reviewed-by: Biju Das <[email protected]> > > Reviewed-by: Geert Uytterhoeven <[email protected]> > > > --- a/drivers/clk/renesas/rzv2h-cpg.c > > +++ b/drivers/clk/renesas/rzv2h-cpg.c > > > +static int rzv2h_cpg_plldsi_div_determine_rate(struct clk_hw *hw, > > + struct clk_rate_request *req) > > +{ > > + struct rzv2h_plldsi_div_clk *dsi_div = to_plldsi_div_clk(hw); > > + struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw)); > > + struct rzv2h_cpg_priv *priv = dsi_div->priv; > > + struct rzv2h_pll_div_pars *dsi_params; > > + struct rzv2h_pll_dsi_info *dsi_info; > > + u64 rate_millihz; > > + > > + dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance]; > > + dsi_params = &dsi_info->pll_dsi_parameters; > > + > > + rate_millihz = mul_u32_u32(req->rate, MILLI); > > + if (rate_millihz == dsi_params->div.error_millihz + > > dsi_params->div.freq_millihz) > > + goto exit_determine_rate; > > + > > + if (!rzv2h_get_pll_dtable_pars(dsi_info->pll_dsi_limits, > > dsi_params, dsi_div->dtable, > > + rate_millihz)) { > > + dev_err(priv->dev, > > + "failed to determine rate for req->rate: %lu\n", > > + req->rate); > > + return -EINVAL; > > + } > > + > > +exit_determine_rate: > > + req->rate = DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millihz, > > MILLI); > > + req->best_parent_rate = req->rate * dsi_params->div.divider_value; > > + dsi_info->req_pll_dsi_rate = req->best_parent_rate; > > + > > + return 0; > > +}; > > Unneeded semicolon (there are three more below). I will fix that. Cheers, Prabhakar
