On 15/10/2025 16:38, Marek Vasut wrote:
> Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
> present in Renesas R-Car R8A77961 M3-W+ SoC.
> 
> Reviewed-by: Niklas Söderlund <[email protected]>
> Signed-off-by: Marek Vasut <[email protected]>

Same as P2/3:

Acked-by: Matt Coster <[email protected]>

Cheers,
Matt

> ---
> Cc: Adam Ford <[email protected]>
> Cc: Conor Dooley <[email protected]>
> Cc: David Airlie <[email protected]>
> Cc: Frank Binns <[email protected]>
> Cc: Geert Uytterhoeven <[email protected]>
> Cc: Krzysztof Kozlowski <[email protected]>
> Cc: Kuninori Morimoto <[email protected]>
> Cc: Maarten Lankhorst <[email protected]>
> Cc: Magnus Damm <[email protected]>
> Cc: Matt Coster <[email protected]>
> Cc: Maxime Ripard <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Simona Vetter <[email protected]>
> Cc: Thomas Zimmermann <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> V2: - Add RB from Niklas
>     - Fix up power-domains = <&sysc R8A77961_PD_3DG_B>; for 77961
>     - Fill in all three clock and two power domains
> ---
>  arch/arm64/boot/dts/renesas/r8a77961.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi 
> b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> index 12435ad9adc04..aa7f5de61e787 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> @@ -2455,6 +2455,22 @@ gic: interrupt-controller@f1010000 {
>                       resets = <&cpg 408>;
>               };
>  
> +             gpu: gpu@fd000000 {
> +                     compatible = "renesas,r8a77961-gpu",
> +                                  "img,img-gx6250",
> +                                  "img,img-rogue";
> +                     reg = <0 0xfd000000 0 0x40000>;
> +                     interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +                     clocks = <&cpg CPG_CORE R8A77961_CLK_ZG>,
> +                              <&cpg CPG_CORE R8A77961_CLK_S2D1>,
> +                              <&cpg CPG_MOD 112>;
> +                     clock-names = "core", "mem", "sys";
> +                     power-domains = <&sysc R8A77961_PD_3DG_A>,
> +                                     <&sysc R8A77961_PD_3DG_B>;
> +                     power-domain-names = "a", "b";
> +                     resets = <&cpg 112>;
> +             };
> +
>               pciec0: pcie@fe000000 {
>                       compatible = "renesas,pcie-r8a77961",
>                                    "renesas,pcie-rcar-gen3";


-- 
Matt Coster
E: [email protected]

Attachment: OpenPGP_signature.asc
Description: OpenPGP digital signature

Reply via email to