On 2025-09-30 at 23:29 +1000, Danilo Krummrich <[email protected]> wrote... > On 9/30/25 3:16 PM, Alistair Popple wrote: > > + // SAFETY: No DMA allocations have been made yet > > + unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<47>())? }; > > I think you forgot to derive the value from the relevant sources, i.e. > physical > bus, DMA controller and MMU capabilities. > > I assume not all GPU architectures / generations have the exact same > capabilities?
Right. Long term we need a HAL for this, and I believe John was going to look at that. In the short term everything we care about supports the same 47-bit address width. And when I say "everything" I mean Turing and Ampere, although I'm pretty sure 47-bits goes back to at least Pascal. Newer GPU architectures (Hopper+) support greater widths (52-bits), but there's no real impact to constraining these for now until a proper HAL is in place. And that sounds like an excellent addition that I should make to the commit logs and/or the comment on the constant definition, which fell off my radar when reworking the rest of this series but will fix for v4.
