On 10/17/2025, Marek Vasut wrote: > On 10/15/25 12:09 PM, Liu Ying wrote: > > Hello Liu,
Hello Marek, > >>>> This has conflicts with my in-flight patch series for adding i.MX8QXP DC >>>> prefetch engine support(though i.MX95 SoC doesn't embed any display >>>> controller >>>> prefetch engine). You probably want to take a look at it, just a heads up. >>>> >>>> https://lore.kernel.org/all/[email protected]/ >>> >>> Thank you for sharing that. >>> >>> Would it make sense to send 4 and 5 separately , so the fixes can land >>> faster? >> >> Maybe not, since there is no user(DT node is not enabled) so far. >> But I'd like to have more review/ack for that patch series(it's kind of >> hard to get sufficient review...). > > I could test on the MX95 if we can somehow ... figure this out. Then I > can provide RB/TB easily. I don't have MX8qxp device. Thanks. Maybe RB is sufficient. TB is something nice to have. > >>> Also, could you please try and avoid the SCU dependency on patch 7 , >>> and more in that direction , can the PRG be made a bit more optional, so the >> >> Don't think there is any way to address them. >> >>> iMX95 can still be supported by the DC driver ? >> >> SCU dependency and PRG(even more other reasons) make me opt to separate >> modules for i.MX95/8qxp DCs. > SCU is only a register accessor, Well, maybe it is. But IIUC the registers are directly accessed by Cortex-M core, not Cortex-A core. See drivers/firmware/imx/Kconfig: config IMX_SCU bool "IMX SCU Protocol driver" depends on IMX_MBOX select SOC_BUS help The System Controller Firmware (SCFW) is a low-level system function which runs on a dedicated Cortex-M core to provide power, clock, and resource management. It exists on some i.MX8 processors. e.g. i.MX8QM (QM, QP), and i.MX8QX (QXP, DX). This driver manages the IPC interface between host CPU and the SCU firmware running on M4. > PRG is another block in the DC, PRG and DPRC are in i.MX8qxp/qm DC subsystem but out of i.MX8qxp/qm DC. > I think those can be isolated. Not sure how to isolate SCU and PRG out of imx8_dc_drm. > It seems the whole DC is a composition of > multiple reusable blocks, so we can compose them for both MX8qxp and > MX95 the right way and reuse most of the code, right ? Some un-reusable blocks would impact how we implement the callbacks to enable/disable CRTC and update/disable planes a lot. I'd expect separate modules(imx8_dc_drm and something like imx95_dc_drm) + imx_dc_drm_common module(which contains reusable code). -- Regards, Liu Ying
