On Mon, Oct 20, 2025 at 02:55:36PM -0400, Joel Fernandes wrote: > +The window position is controlled via the PBUS BAR0_WINDOW register:: > + > + NV_PBUS_BAR0_WINDOW Register > + +-----+-----+--------------------------------------+ > + |31-26|25-24| 23-0 | > + | |TARG | BASE_ADDR | > + | | ET | (bits 39:16 of VRAM address) | > + +-----+-----+--------------------------------------+
Shouldn't the TARGET field cell above be fitted (extended)?
> +
> + TARGET field values:
> + - 0x0: VID_MEM (Video Memory / VRAM)
> + - 0x1: SYS_MEM_COHERENT (Coherent system memory)
> + - 0x2: SYS_MEM_NONCOHERENT (Non-coherent system memory)
> +
> +64KB Alignment Requirement
> +---------------------------
> +
> +The PRAMIN window must be aligned to 64KB boundaries in VRAM. This is
> enforced
> +by the BASE_ADDR field representing bits [39:16] of the target address::
> +
> + VRAM Address Calculation:
> + actual_vram_addr = (BASE_ADDR << 16) + pramin_offset
> + Where:
> + - BASE_ADDR: 24-bit value from NV_PBUS_BAR0_WINDOW[23:0]
> + - pramin_offset: 20-bit offset within PRAMIN window [0x00000-0xFFFFF]
> + Example Window Positioning:
Move the supplementary explanation out of respective literal code blocks,
like::
---- >8 ----
diff --git a/Documentation/gpu/nova/core/pramin.rst
b/Documentation/gpu/nova/core/pramin.rst
index 19615e504db9d5..47abe539e32a81 100644
--- a/Documentation/gpu/nova/core/pramin.rst
+++ b/Documentation/gpu/nova/core/pramin.rst
@@ -70,23 +70,28 @@ The window position is controlled via the PBUS BAR0_WINDOW
register::
| | ET | (bits 39:16 of VRAM address) |
+-----+-----+--------------------------------------+
- TARGET field values:
- - 0x0: VID_MEM (Video Memory / VRAM)
- - 0x1: SYS_MEM_COHERENT (Coherent system memory)
- - 0x2: SYS_MEM_NONCOHERENT (Non-coherent system memory)
+where TARGET field values are:
+
+ - 0x0: VID_MEM (Video Memory / VRAM)
+ - 0x1: SYS_MEM_COHERENT (Coherent system memory)
+ - 0x2: SYS_MEM_NONCOHERENT (Non-coherent system memory)
64KB Alignment Requirement
---------------------------
The PRAMIN window must be aligned to 64KB boundaries in VRAM. This is enforced
-by the BASE_ADDR field representing bits [39:16] of the target address::
+by the BASE_ADDR field representing bits [39:16] of the target address. The
+VRAM address calculation is determined by::
- VRAM Address Calculation:
actual_vram_addr = (BASE_ADDR << 16) + pramin_offset
- Where:
- - BASE_ADDR: 24-bit value from NV_PBUS_BAR0_WINDOW[23:0]
- - pramin_offset: 20-bit offset within PRAMIN window [0x00000-0xFFFFF]
- Example Window Positioning:
+
+where:
+
+ - BASE_ADDR: 24-bit value from NV_PBUS_BAR0_WINDOW[23:0]
+ - pramin_offset: 20-bit offset within PRAMIN window [0x00000-0xFFFFF]
+
+Example window positioning::
+
+---------------------------------------------------------+
| VRAM Space |
| |
Thanks.
--
An old man doll... just what I always wanted! - Clara
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