On 10/21/25 21:50, Greg Kroah-Hartman wrote: > 6.17-stable review patch. If anyone has any objections, please let me know. > > ------------------ > > From: Thomas Zimmermann <[email protected]> > > commit 6f719373b943a955fee6fc2012aed207b65e2854 upstream. > > Blank the display by disabling sync pulses with VGACR17<7>. Unblank > by reenabling them. This VGA setting should be supported by all Aspeed > hardware.
TWIMC, a regression report about 6.18-rc2 that was bisected to this commit just came in: https://lore.kernel.org/all/[email protected]/ To quote: """ I have encountered a serious (for me) regression with 6.18-rc2 on my 2-socket Ivy Bridge Xeon E5-2697 v2 server. After booting, my console screen goes blank and stays blank. 6.18-rc1 was still fine. [...] When I revert this from 6.18-rc2, the issue goes away and my console screen works again. """ Ciao, Thorsten > Ast currently blanks via sync-off bits in VGACRB6. Not all BMCs handle > VGACRB6 correctly. After disabling sync during a reboot, some BMCs do > not reenable it after the soft reset. The display output remains dark. > When the display is off during boot, some BMCs set the sync-off bits in > VGACRB6, so the display remains dark. Observed with Blackbird AST2500 > BMCs. Clearing the sync-off bits unconditionally fixes these issues. > > Also do not modify VGASR1's SD bit for blanking, as it only disables GPU > access to video memory. > > v2: > - init vgacrb6 correctly (Jocelyn) > > Signed-off-by: Thomas Zimmermann <[email protected]> > Fixes: ce3d99c83495 ("drm: Call drm_atomic_helper_shutdown() at shutdown time > for misc drivers") > Tested-by: Nick Bowler <[email protected]> > Reported-by: Nick Bowler <[email protected]> > Closes: > https://lore.kernel.org/dri-devel/wpwd7rit6t4mnu6kdqbtsnk5bhftgslio6e2jgkz6kgw6cuvvr@xbfswsczfqsi/ > Cc: Douglas Anderson <[email protected]> > Cc: Dave Airlie <[email protected]> > Cc: Thomas Zimmermann <[email protected]> > Cc: Jocelyn Falempe <[email protected]> > Cc: [email protected] > Cc: <[email protected]> # v6.7+ > Reviewed-by: Jocelyn Falempe <[email protected]> > Link: https://lore.kernel.org/r/[email protected] > Signed-off-by: Greg Kroah-Hartman <[email protected]> > --- > drivers/gpu/drm/ast/ast_mode.c | 18 ++++++++++-------- > drivers/gpu/drm/ast/ast_reg.h | 1 + > 2 files changed, 11 insertions(+), 8 deletions(-) > > --- a/drivers/gpu/drm/ast/ast_mode.c > +++ b/drivers/gpu/drm/ast/ast_mode.c > @@ -836,22 +836,24 @@ ast_crtc_helper_atomic_flush(struct drm_ > static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct > drm_atomic_state *state) > { > struct ast_device *ast = to_ast_device(crtc->dev); > + u8 vgacr17 = 0x00; > + u8 vgacrb6 = 0xff; > > - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, 0x00); > - ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, 0x00); > + vgacr17 |= AST_IO_VGACR17_SYNC_ENABLE; > + vgacrb6 &= ~(AST_IO_VGACRB6_VSYNC_OFF | AST_IO_VGACRB6_HSYNC_OFF); > + > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); > } > > static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct > drm_atomic_state *state) > { > struct drm_crtc_state *old_crtc_state = > drm_atomic_get_old_crtc_state(state, crtc); > struct ast_device *ast = to_ast_device(crtc->dev); > - u8 vgacrb6; > + u8 vgacr17 = 0xff; > > - ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, > AST_IO_VGASR1_SD); > - > - vgacrb6 = AST_IO_VGACRB6_VSYNC_OFF | > - AST_IO_VGACRB6_HSYNC_OFF; > - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); > + vgacr17 &= ~AST_IO_VGACR17_SYNC_ENABLE; > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); > > /* > * HW cursors require the underlying primary plane and CRTC to > --- a/drivers/gpu/drm/ast/ast_reg.h > +++ b/drivers/gpu/drm/ast/ast_reg.h > @@ -29,6 +29,7 @@ > #define AST_IO_VGAGRI (0x4E) > > #define AST_IO_VGACRI (0x54) > +#define AST_IO_VGACR17_SYNC_ENABLE BIT(7) /* called "Hardware reset" in > docs */ > #define AST_IO_VGACR80_PASSWORD (0xa8) > #define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0) > #define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1) > > >
