On Mon, Oct 27, 2025 at 02:09:48PM +0100, Neil Armstrong wrote:
> When in bonded DSI mode, only one PLL in one DSI PHY is used for both
> DSI PHYs, meaning that parents of the secondary DSI PHY will use the
> primary DSI PHY PLL as parent.
>
> In this case the primary DSI PHY PLL will be set even if the primary
> DSI PHY is not yet enabled. The DSI PHY code has support for this
> particular use-case and will handle the fact the PLL was already
> set when initializing the primary DSI PHY.
>
> By introducing a protected variable pll_enable_cnt in the commit
> cb55f39bf7b1 ("drm/msm/dsi/phy: Fix reading zero as PLL rates when
> unprepared"),
> this variable is only initially set to 1 when the DSI PHY is initialized
> making it impossible to set the PLL before, breaking the bonded DSI
> use case by returning 0 when setting the PLL from the secondary DSI
> PHY driver and skipping the correct clocks initialization.
>
> But since it was already possible to set the PLL without enabling
> the DSI PHY, just drop the pll_enable_cnt setting from the PHY
> enable/disable and simply increment/decrement the pll_enable_cnt
> variable from the dsi_pll_enable/disable_pll_bias to make sure any
> PLL operation is done with the PLL BIAS enabled.
>
> Fixes: cb55f39bf7b1 ("drm/msm/dsi/phy: Fix reading zero as PLL rates when
> unprepared")
> Closes:
> https://lore.kernel.org/all/[email protected]/
> Tested-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 -
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 18 ++----------------
> 2 files changed, 2 insertions(+), 17 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
