The Leadtek LTK08QV25BYL is a 2.8" 240x320 DSI display.
Signed-off-by: Herve Codina <[email protected]>
---
drivers/gpu/drm/panel/Kconfig | 12 +
drivers/gpu/drm/panel/Makefile | 1 +
.../drm/panel/panel-leadtek-ltk028qv25byl.c | 304 ++++++++++++++++++
3 files changed, 317 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-leadtek-ltk028qv25byl.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 407c5f6a268b..faa417195b6e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -367,6 +367,18 @@ config DRM_PANEL_KINGDISPLAY_KD097D04
24 bit RGB per pixel. It provides a MIPI DSI interface to
the host and has a built-in LED backlight.
+config DRM_PANEL_LEADTEK_LTK028QV25BYL
+ tristate "Leadtek LTK028QV25BYL panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for Leadtek LTK028QV25BYL
+ TFT-LCD modules. The panel has a 240x320 resolution and uses
+ 18 bit RGB per pixel. It provides a MIPI DSI interface to
+ the host and has a built-in LED backlight.
+
+
config DRM_PANEL_LEADTEK_LTK050H3146W
tristate "Leadtek LTK050H3146W panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 3615a761b44f..12073c34e0f5 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_DRM_PANEL_JDI_LPM102A188A) +=
panel-jdi-lpm102a188a.o
obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o
obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o
obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
+obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK028QV25BYL) += panel-leadtek-ltk028qv25byl.o
obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o
obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LINCOLNTECH_LCD197) += panel-lincolntech-lcd197.o
diff --git a/drivers/gpu/drm/panel/panel-leadtek-ltk028qv25byl.c
b/drivers/gpu/drm/panel/panel-leadtek-ltk028qv25byl.c
new file mode 100644
index 000000000000..2e3482b2b95c
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-leadtek-ltk028qv25byl.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Leadtek LTK08QV25BYL 2.8" MIPI-DSI panel driver
+ * Copyright (c) 2025, Bootlin
+ *
+ * base on panel-leadtek-ltk050h346w.c
+ * Copyright (C) 2020 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+struct ltk028qv25byl {
+ struct device *dev;
+ struct drm_panel panel;
+ struct gpio_desc *reset_gpio;
+ struct regulator *vci;
+ struct regulator *iovcc;
+};
+
+static inline struct ltk028qv25byl *panel_to_ltk028qv25byl(struct drm_panel
*panel)
+{
+ return container_of(panel, struct ltk028qv25byl, panel);
+}
+
+static int ltk028qv25byl_init_sequence(struct ltk028qv25byl *ctx)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
+
+ /*
+ * Init sequence was supplied by the panel vendor. All documentation
+ * provided by the vendor (i.e comments in the provided init sequence)
+ * is also given here as comments without modification.
+ */
+
+ /* Password */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdf, 0x98, 0x51, 0xe9);
+
+ /* Page 0 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x00);
+
+ /* VGMP, VGSP, VGMN, VGSN 4.3 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb7, 0x1e, 0x85, 0x1e, 0x33);
+
+ /* Set_R_GAMMA */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8, 0x3f, 0x2e, 0x25, 0x21,
0x23,
+ 0x25, 0x1f, 0x1e, 0x1c, 0x1b, 0x19, 0x11,
+ 0x0e, 0x0a, 0x06, 0x0e, 0x3f, 0x2e, 0x26,
+ 0x21, 0x24, 0x25, 0x1f, 0x1f, 0x1d, 0x1c,
+ 0x19, 0x11, 0x0e, 0x0a, 0x06, 0x0e);
+
+ /* POW_CTRL */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x33, 0x08, 0xcc);
+
+ /* DCDC_SEL */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbb, 0x44, 0x7a, 0x30, 0x40,
0x7c,
+ 0x60, 0x70, 0x70);
+
+ /* VDD_CTRL */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbc, 0x38, 0x3c);
+
+ /* SETSTBA */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0, 0x31, 0x20);
+
+ /* SETPANEL(default) */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x12);
+
+ /* SETRGBCYC */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3, 0x08, 0x00, 0x0a, 0x10,
0x08,
+ 0x54, 0x45, 0x71, 0x2c);
+
+ /* SETRGBCYC(default) */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, 0x00, 0xa0, 0x79, 0x0e,
0x0a,
+ 0x16, 0x79, 0x0e, 0x0a, 0x16, 0x79, 0x0e,
+ 0x0a, 0x16, 0x82, 0x00, 0x03);
+
+ /* SET_GD(default) */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd0, 0x04, 0x0c, 0x6a, 0x0f,
0x00, 0x03);
+
+ /* RAMCTRL(default) */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd7, 0x13, 0x00);
+
+ /* Page 2 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x02);
+
+ /* DCDC_SET */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x1d, 0xa0, 0x2f, 0x2c,
0x2b);
+
+ /* SETRGBCYC2 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x10, 0x66, 0x66, 0x01);
+
+ /* Page 0 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x00);
+
+ /* SLPOUT + 120ms delay */
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+
+ /* Page 2 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x02);
+
+ /* OSCM */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc5, 0x4e, 0x00, 0x00);
+
+ /* SETMIPI_2 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0x30, 0x20, 0xf4);
+
+ /* Page 4 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x04);
+
+ /* SETPHY3 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd3, 0x3c);
+
+ /* Page 0 */
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x00);
+
+ /* Display on + 20ms delay */
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 20);
+
+ return dsi_ctx.accum_err;
+}
+
+static int ltk028qv25byl_unprepare(struct drm_panel *panel)
+{
+ struct ltk028qv25byl *ctx = panel_to_ltk028qv25byl(panel);
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
+
+ mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+ mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+ if (dsi_ctx.accum_err)
+ return dsi_ctx.accum_err;
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+
+ regulator_disable(ctx->iovcc);
+ regulator_disable(ctx->vci);
+
+ return 0;
+}
+
+static int ltk028qv25byl_prepare(struct drm_panel *panel)
+{
+ struct ltk028qv25byl *ctx = panel_to_ltk028qv25byl(panel);
+ int ret;
+
+ ret = regulator_enable(ctx->vci);
+ if (ret < 0) {
+ dev_err(ctx->dev, "Failed to enable vcc supply (%d)\n", ret);
+ return ret;
+ }
+ ret = regulator_enable(ctx->iovcc);
+ if (ret < 0) {
+ dev_err(ctx->dev, "Failed to enable iovcc supply (%d)\n", ret);
+ goto disable_vci;
+ }
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ usleep_range(5000, 6000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(20);
+
+ ret = ltk028qv25byl_init_sequence(ctx);
+ if (ret)
+ goto force_reset;
+
+ return 0;
+
+force_reset:
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ regulator_disable(ctx->iovcc);
+disable_vci:
+ regulator_disable(ctx->vci);
+ return ret;
+}
+
+static const struct drm_display_mode ltk028qv25byl_mode = {
+ .hdisplay = 240,
+ .hsync_start = 240 + 120,
+ .hsync_end = 240 + 120 + 4,
+ .htotal = 240 + 120 + 4 + 120,
+ .vdisplay = 320,
+ .vsync_start = 320 + 8,
+ .vsync_end = 320 + 8 + 2,
+ .vtotal = 320 + 8 + 2 + 6,
+ .clock = 10000000 / 1000,
