Implement core resume operation. This is the last step of the sequencer resulting in resume of the GSP and proceeding to INIT_DONE stage of GSP boot.
Signed-off-by: Joel Fernandes <[email protected]> --- drivers/gpu/nova-core/falcon/gsp.rs | 1 - drivers/gpu/nova-core/gsp/fw.rs | 1 - drivers/gpu/nova-core/gsp/sequencer.rs | 49 ++++++++++++++++++++++++-- 3 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/falcon/gsp.rs index e0c0b18ec5bf..391699dc3a8c 100644 --- a/drivers/gpu/nova-core/falcon/gsp.rs +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -37,7 +37,6 @@ pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { } /// Checks if GSP reload/resume has completed during the boot process. - #[expect(dead_code)] pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> { read_poll_timeout( || Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar)), diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs index 53e28458cd7d..bb79f92432aa 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -543,7 +543,6 @@ pub(crate) fn element_count(&self) -> u32 { } } -#[expect(unused)] pub(crate) use r570_144::{ // GSP sequencer run structure with information on how to run the sequencer. rpc_run_cpu_sequencer_v17_00, diff --git a/drivers/gpu/nova-core/gsp/sequencer.rs b/drivers/gpu/nova-core/gsp/sequencer.rs index 127b293a161c..ecc80f668dc8 100644 --- a/drivers/gpu/nova-core/gsp/sequencer.rs +++ b/drivers/gpu/nova-core/gsp/sequencer.rs @@ -52,6 +52,7 @@ pub(crate) enum GspSeqCmd { CoreReset, CoreStart, CoreWaitForHalt, + CoreResume, } impl GspSeqCmd { @@ -83,6 +84,7 @@ pub(crate) fn from_fw_cmd(cmd: &fw::GSP_SEQUENCER_BUFFER_CMD) -> Result<Self> { fw::GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT => { Ok(GspSeqCmd::CoreWaitForHalt) } + fw::GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_RESUME => Ok(GspSeqCmd::CoreResume), _ => Err(EINVAL), } } @@ -105,7 +107,10 @@ pub(crate) fn size_bytes(&self) -> usize { let opcode_size = size_of::<fw::GSP_SEQ_BUF_OPCODE>(); match self { // Each simple command type just adds 4 bytes (opcode_size) for the header. - GspSeqCmd::CoreReset | GspSeqCmd::CoreStart | GspSeqCmd::CoreWaitForHalt => opcode_size, + GspSeqCmd::CoreReset + | GspSeqCmd::CoreStart + | GspSeqCmd::CoreWaitForHalt + | GspSeqCmd::CoreResume => opcode_size, // For commands with payloads, add the payload size in bytes. GspSeqCmd::RegWrite(_) => opcode_size + size_of::<fw::GSP_SEQ_BUF_PAYLOAD_REG_WRITE>(), @@ -119,7 +124,6 @@ pub(crate) fn size_bytes(&self) -> usize { } } -#[expect(dead_code)] pub(crate) struct GspSequencer<'a> { seq_info: GspSequencerInfo<'a>, bar: &'a Bar0, @@ -259,6 +263,47 @@ fn run(&self, seq: &GspSequencer<'_>) -> Result { seq.gsp_falcon.wait_till_halted(seq.bar)?; Ok(()) } + GspSeqCmd::CoreResume => { + dev_dbg!(seq.dev, "CoreResume\n"); + // At this point, 'SEC2-RTOS' has been loaded into SEC2 by the sequencer + // but neither SEC2-RTOS nor GSP-RM is running yet. This part of the + // sequencer will start both. + + // Reset the GSP to prepare it for resuming. + seq.gsp_falcon.reset(seq.bar)?; + + // Write the libOS DMA handle to GSP mailboxes. + seq.gsp_falcon.write_mailboxes( + seq.bar, + Some(seq.libos_dma_handle as u32), + Some((seq.libos_dma_handle >> 32) as u32), + )?; + + // Start the SEC2 falcon which will trigger GSP-RM to resume on the GSP. + seq.sec2_falcon.start(seq.bar)?; + + // Poll until GSP-RM reload/resume has completed (up to 2 seconds). + seq.gsp_falcon + .check_reload_completed(seq.bar, Delta::from_secs(2))?; + + // Verify SEC2 completed successfully by checking its mailbox for errors. + let mbox0 = seq.sec2_falcon.read_mailbox0(seq.bar)?; + if mbox0 != 0 { + dev_err!(seq.dev, "Sequencer: sec2 errors: {:?}\n", mbox0); + return Err(EIO); + } + + // Configure GSP with the bootloader version. + seq.gsp_falcon + .write_os_version(seq.bar, seq.gsp_fw.bootloader.app_version); + + // Verify the GSP's RISC-V core is active indicating successful GSP boot. + if !seq.gsp_falcon.is_riscv_active(seq.bar) { + dev_err!(seq.dev, "Sequencer: RISC-V core is not active\n"); + return Err(EIO); + } + Ok(()) + } } } } -- 2.34.1
