On 11/7/25 10:04, Pierre-Eric Pelloux-Prayer wrote: > If true, the hw engine retains context among dependent jobs, which means > load balancing between schedulers cannot be used at the job level.
Take the sentence above... > > amdgpu_ctx_init_entity uses this information to disable load balancing, > but it's best to store it as a property rather than deduce it based on > hw_ip. > > Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 3 +++ > drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 3 +++ > drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 1 + > 15 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > index 4b46e3c26ff3..a10efac2fc54 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > @@ -211,6 +211,7 @@ struct amdgpu_ring_funcs { > bool support_64bit_ptrs; > bool no_user_fence; > bool secure_submission_supported; > + bool engine_retains_context; ... and put it as kerneldoc (similar to @extra_bytes below) here on the member. With that done the patch is Reviewed-by: Christian König <[email protected]> Regards, Christian. > > /** > * @extra_bytes: > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c > index 2e79a3afc774..4a85b5465bb2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c > @@ -181,6 +181,7 @@ static const struct amdgpu_ring_funcs uvd_v3_1_ring_funcs > = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v3_1_ring_get_rptr, > .get_wptr = uvd_v3_1_ring_get_wptr, > .set_wptr = uvd_v3_1_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > index 4b96fd583772..e7c1d12f0596 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > @@ -775,6 +775,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs > = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v4_2_ring_get_rptr, > .get_wptr = uvd_v4_2_ring_get_wptr, > .set_wptr = uvd_v4_2_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > index 71409ad8b7ed..a62788e4af96 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > @@ -882,6 +882,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs > = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v5_0_ring_get_rptr, > .get_wptr = uvd_v5_0_ring_get_wptr, > .set_wptr = uvd_v5_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index ceb94bbb03a4..0435577b9b3b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -1552,6 +1552,7 @@ static const struct amdgpu_ring_funcs > uvd_v6_0_ring_phys_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v6_0_ring_get_rptr, > .get_wptr = uvd_v6_0_ring_get_wptr, > .set_wptr = uvd_v6_0_ring_set_wptr, > @@ -1578,6 +1579,7 @@ static const struct amdgpu_ring_funcs > uvd_v6_0_ring_vm_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v6_0_ring_get_rptr, > .get_wptr = uvd_v6_0_ring_get_wptr, > .set_wptr = uvd_v6_0_ring_set_wptr, > @@ -1607,6 +1609,7 @@ static const struct amdgpu_ring_funcs > uvd_v6_0_enc_ring_vm_funcs = { > .nop = HEVC_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v6_0_enc_ring_get_rptr, > .get_wptr = uvd_v6_0_enc_ring_get_wptr, > .set_wptr = uvd_v6_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > index 1f8866f3f63c..3720d72f2c3e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > @@ -1539,6 +1539,7 @@ static const struct amdgpu_ring_funcs > uvd_v7_0_ring_vm_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v7_0_ring_get_rptr, > .get_wptr = uvd_v7_0_ring_get_wptr, > .set_wptr = uvd_v7_0_ring_set_wptr, > @@ -1571,6 +1572,7 @@ static const struct amdgpu_ring_funcs > uvd_v7_0_enc_ring_vm_funcs = { > .nop = HEVC_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v7_0_enc_ring_get_rptr, > .get_wptr = uvd_v7_0_enc_ring_get_wptr, > .set_wptr = uvd_v7_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index a316797875a8..1691d0f955a9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -2117,6 +2117,7 @@ static const struct amdgpu_ring_funcs > vcn_v1_0_dec_ring_vm_funcs = { > .support_64bit_ptrs = false, > .no_user_fence = true, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v1_0_dec_ring_get_rptr, > .get_wptr = vcn_v1_0_dec_ring_get_wptr, > .set_wptr = vcn_v1_0_dec_ring_set_wptr, > @@ -2150,6 +2151,7 @@ static const struct amdgpu_ring_funcs > vcn_v1_0_enc_ring_vm_funcs = { > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > + .engine_retains_context = true, > .no_user_fence = true, > .get_rptr = vcn_v1_0_enc_ring_get_rptr, > .get_wptr = vcn_v1_0_enc_ring_get_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > index 8897dcc9c1a0..046dd6b216e9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > @@ -2113,6 +2113,7 @@ static const struct amdgpu_ring_funcs > vcn_v2_0_dec_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_DEC, > .align_mask = 0xf, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v2_0_dec_ring_get_rptr, > .get_wptr = vcn_v2_0_dec_ring_get_wptr, > .set_wptr = vcn_v2_0_dec_ring_set_wptr, > @@ -2144,6 +2145,7 @@ static const struct amdgpu_ring_funcs > vcn_v2_0_enc_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v2_0_enc_ring_get_rptr, > .get_wptr = vcn_v2_0_enc_ring_get_wptr, > .set_wptr = vcn_v2_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > index cebee453871c..063f88da120b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > @@ -1777,6 +1777,7 @@ static const struct amdgpu_ring_funcs > vcn_v2_5_dec_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_DEC, > .align_mask = 0xf, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v2_5_dec_ring_get_rptr, > .get_wptr = vcn_v2_5_dec_ring_get_wptr, > .set_wptr = vcn_v2_5_dec_ring_set_wptr, > @@ -1877,6 +1878,7 @@ static const struct amdgpu_ring_funcs > vcn_v2_5_enc_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v2_5_enc_ring_get_rptr, > .get_wptr = vcn_v2_5_enc_ring_get_wptr, > .set_wptr = vcn_v2_5_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c > index d9cf8f0feeb3..8dcc07b3f631 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c > @@ -1857,6 +1857,7 @@ static const struct amdgpu_ring_funcs > vcn_v3_0_dec_sw_ring_vm_funcs = { > .align_mask = 0x3f, > .nop = VCN_DEC_SW_CMD_NO_OP, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v3_0_dec_ring_get_rptr, > .get_wptr = vcn_v3_0_dec_ring_get_wptr, > .set_wptr = vcn_v3_0_dec_ring_set_wptr, > @@ -2021,6 +2022,7 @@ static const struct amdgpu_ring_funcs > vcn_v3_0_dec_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_DEC, > .align_mask = 0xf, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v3_0_dec_ring_get_rptr, > .get_wptr = vcn_v3_0_dec_ring_get_wptr, > .set_wptr = vcn_v3_0_dec_ring_set_wptr, > @@ -2122,6 +2124,7 @@ static const struct amdgpu_ring_funcs > vcn_v3_0_enc_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v3_0_enc_ring_get_rptr, > .get_wptr = vcn_v3_0_enc_ring_get_wptr, > .set_wptr = vcn_v3_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > index 3ae666522d57..f1306316dc3c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > @@ -1977,6 +1977,7 @@ static struct amdgpu_ring_funcs > vcn_v4_0_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata), > .get_rptr = vcn_v4_0_unified_ring_get_rptr, > .get_wptr = vcn_v4_0_unified_ring_get_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > index eacf4e93ba2f..5a935c07352a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > @@ -1628,6 +1628,7 @@ static const struct amdgpu_ring_funcs > vcn_v4_0_3_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, > .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, > .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > index b107ee80e472..1a485f5825dd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > @@ -1481,6 +1481,7 @@ static struct amdgpu_ring_funcs > vcn_v4_0_5_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, > .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, > .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > index 0202df5db1e1..2d8214f591f1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > @@ -1203,6 +1203,7 @@ static const struct amdgpu_ring_funcs > vcn_v5_0_0_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, > .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, > .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > index 714350cabf2f..bd3a04f1414d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > @@ -1328,6 +1328,7 @@ static const struct amdgpu_ring_funcs > vcn_v5_0_1_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, > .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, > .set_wptr = vcn_v5_0_1_unified_ring_set_wptr,
