Dear Paul, On 6/25/25 10:41 AM, Paul Kocialkowski wrote: > Hi, > > Thanks for your work on this! > > On Fri 27 Dec 24, 16:38, Parthiban Nallathambi wrote: >> DPHY in A100/A133 supports both LVDS and DSI. Combo phy register >> have BIT(2) for enabling LVDS specifically, but enabling it alone >> isn't functional. >> >> Both MIPI and LVDS needs to be enabled in the combo phy to get >> the display working under LVDS mode. There is no specific enable >> bit for LVDS apart from the one in combo phy. MIPI got enable >> control in analog 4 register which must be disabled when using >> in LVDS mode. >> >> Introduce set_mode in phy ops to control only for MIPI DSI. > Similar work was already submitted for D1/T113-S3 LVDS support, which seems to > be the exact same situation as the A133. > > See: https://patchwork.freedesktop.org/series/145276/ > > I just made a review of that series and find it more elegant in various ways > (especially since configuring the registers in set_mode is not the right > place). > So you probably want to follow-up on that series instead. > > Note that both D1/T113-S3 and A133 support a second LVDS output, LVDS1, which > uses the traditional TCON0 LVDS PHY. It would be great to be able to support > both outputs as well as dual-link modes!
I have addressed the remaining part of the comments except this one. I will wait for the other series to be addressed by Kuba or if not I will pick to my tree and try to address it. Does it makes sense to wait for that series to get merged / addressed or it makes sense post my series for further review? My previous push was largely complete because of mail server issues which I have fixed now and ready to push. Thanks, Parthiban> > All the best, > > Paul
