> Subject: [PATCH v3 08/10] drm/i915/alpm: Enable MAC Transmitting LFPS for > LT phy
* PHY > > Enable MAC to transmit LFPS via LT phy during aux-less alpm. * PHY > > v2: > - Correct commit description. [Suraj] > - Remove loop as no dependency on the transmitter LT_PHY_CMN_CTL0. > [Suraj] > > Cc: Jouni Högander <[email protected]> > Signed-off-by: Animesh Manna <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++- > drivers/gpu/drm/i915/display/intel_lt_phy.c | 26 +++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 ++ > .../gpu/drm/i915/display/intel_lt_phy_regs.h | 3 +++ > 4 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 733ef4559131..f6450ebea2a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3781,7 +3781,10 @@ static void mtl_ddi_prepare_link_retrain(struct > intel_dp *intel_dp, > * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" > PIPE > * register > */ > - intel_lnl_mac_transmit_lfps(encoder, crtc_state); > + if (HAS_LT_PHY(display)) > + intel_xe3plpd_mac_transmit_lfps(encoder, crtc_state); > + else > + intel_lnl_mac_transmit_lfps(encoder, crtc_state); > } > > static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, diff > --git > a/drivers/gpu/drm/i915/display/intel_lt_phy.c > b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index b2413b385dc8..f3258ce98b3f 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -7,6 +7,7 @@ > > #include "i915_reg.h" > #include "i915_utils.h" > +#include "intel_alpm.h" > #include "intel_cx0_phy.h" > #include "intel_cx0_phy_regs.h" > #include "intel_ddi.h" > @@ -2328,3 +2329,28 @@ void intel_xe3plpd_pll_disable(struct > intel_encoder *encoder) > intel_lt_phy_pll_disable(encoder); > > } > + > +/* > + * According to HAS we need to enable MAC Transmitting LFPS in the "PHY > +Common > + * Control 0" PIPE register in case of AUX Less ALPM is going to be > +used. This > + * function is doing that and is called by link retrain sequence. > + */ > +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > + intel_wakeref_t wakeref; > + u8 owned_lane_mask; > + > + if (!intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), Have an encoder variable avoid inlining arguments like this With these fixed Reviewed-by: Suraj Kandpal <[email protected]> > crtc_state)) > + return; > + > + wakeref = intel_lt_phy_transaction_begin(encoder); > + > + owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); > + > + intel_lt_phy_rmw(encoder, owned_lane_mask, LT_PHY_CMN_CTL_0, > + LT_PHY_CMN_LFPS_ENABLE, > + LT_PHY_CMN_LFPS_ENABLE, > MB_WRITE_COMMITTED); > + > + intel_lt_phy_transaction_end(encoder, wakeref); } > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h > b/drivers/gpu/drm/i915/display/intel_lt_phy.h > index b7911acd7dcd..5cea01b1756a 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h > @@ -41,6 +41,8 @@ intel_lt_phy_calculate_hdmi_state(struct > intel_lt_phy_pll_state *lt_state, void intel_xe3plpd_pll_enable(struct > intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); void > intel_xe3plpd_pll_disable(struct intel_encoder *encoder); > +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state); > > #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35) > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h > index 98ccc069a69b..c50dbad28b78 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h > @@ -35,6 +35,9 @@ > #define LT_PHY_TXY_CTL10_MAC(idx) _MMIO(LT_PHY_TXY_CTL10(idx)) > #define LT_PHY_TX_LANE_ENABLE REG_BIT8(0) > > +#define LT_PHY_CMN_CTL_0 (0x800) > +#define LT_PHY_CMN_LFPS_ENABLE REG_BIT8(1) > + > /* LT Phy Vendor Register */ > #define LT_PHY_VDR_0_CONFIG 0xC02 > #define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7) > -- > 2.29.0
