On 11/12/2025 4:07 PM, Konrad Dybcio wrote:
> On 11/10/25 5:37 PM, Akhil P Oommen wrote:
>> GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF
>> configurations before GMU wakes up. This was not a problem so far, but
>> A840 GPU is very sensitive to this requirement. Also, move these
>> registers to the catalog.
>>
>> Signed-off-by: Akhil P Oommen <[email protected]>
>> ---
>
> [...]
>
>> + /* For A7x and newer, do the CX GBIF configurations before GMU wake up
>> */
>> + for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++)
>> + gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value);
>
> We haven't been doing this a lot in the GPU driver, but adding a
> .num_entries-like field is both more memory efficient and less error-prone
Gbif config array is reused a lot. So this is more memory efficient in
this particular case. But generally I agree, we should stick to one
scheme. We can revisit this later.
>
>> +
>> + /* For A7x and newer, do the CX GBIF configurations before GMU wake up
>> */
>
> duplicate comment
>
>> + if (adreno_is_a8xx(adreno_gpu)) {
>> + gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);
>> + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
>
> Either set this prio value here, or in a8xx_gpu.c
We should remove the other one.
>
>> + }
>> +
>> /* Set up the lowest idle level on the GMU */
>> a6xx_gmu_power_config(gmu);
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index 029f7bd25baf..66771958edb2 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -1265,17 +1265,20 @@ static int hw_init(struct msm_gpu *gpu)
>> /* enable hardware clockgating */
>> a6xx_set_hwcg(gpu, true);
>>
>> - /* VBIF/GBIF start*/
>> - if (adreno_is_a610_family(adreno_gpu) ||
>> - adreno_is_a640_family(adreno_gpu) ||
>> - adreno_is_a650_family(adreno_gpu) ||
>> - adreno_is_a7xx(adreno_gpu)) {
>> + /* For gmuwrapper implementations, do the VBIF/GBIF CX configuration
>> here */
>> + if (adreno_is_a610_family(adreno_gpu)) {
>> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
>
> a640/650 family GPUs didn't receive a .gbif_cx addition in the catalog to
> match>
Oops, I missed that. Will fix this. Thanks.
>> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
>> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
>> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
>> - gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
>> - adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3);
>> + }
>> +
>> + if (adreno_is_a610_family(adreno_gpu) ||
>> + adreno_is_a640_family(adreno_gpu) ||
>> + adreno_is_a650_family(adreno_gpu)) {
>> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
>> + } else if (adreno_is_a7xx(adreno_gpu)) {
>> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212);
>> } else {
>> gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
>
> Downstream seems to set QOS_CNTL at the same time as QSB_SIDEn for
> these targets
This register is under GX power domain, so we can't configure this
early. This should be okay.
>
>
>> }
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> index 031ca0e4b689..cf700f7de09b 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> @@ -46,6 +46,7 @@ struct a6xx_info {
>> const struct adreno_protect *protect;
>> const struct adreno_reglist_list *pwrup_reglist;
>> const struct adreno_reglist_list *ifpc_reglist;
>> + const struct adreno_reglist *gbif_cx;
>> const struct adreno_reglist_pipe *nonctxt_reglist;
>> u32 gmu_chipid;
>> u32 gmu_cgc_mode;
>> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> index 2ef69161f1d0..ad140b0d641d 100644
>> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> @@ -500,6 +500,9 @@ static int hw_init(struct msm_gpu *gpu)
>>
>> gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
>>
>> + /* Increase priority of GMU traffic over GPU traffic */
>> + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
>
> Kgsl (later) added this for A740 too - would it be beneficial to enable
> unconditionally on gen7+?
These are actually recommendations coming from HW designers for each
chipset. So we should just stick to that. I will check separately about
a740.
-Akhil.
>
> Konrad
