Implement core resume operation. This is the last step of the sequencer resulting in resume of the GSP and proceeding to INIT_DONE stage of GSP boot.
Signed-off-by: Joel Fernandes <[email protected]> --- drivers/gpu/nova-core/falcon/gsp.rs | 1 - drivers/gpu/nova-core/gsp/sequencer.rs | 44 ++++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/falcon/gsp.rs index 9ef1fbae141f..67edef3636c1 100644 --- a/drivers/gpu/nova-core/falcon/gsp.rs +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -45,7 +45,6 @@ pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { } /// Checks if GSP reload/resume has completed during the boot process. - #[expect(dead_code)] pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> { read_poll_timeout( || Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar)), diff --git a/drivers/gpu/nova-core/gsp/sequencer.rs b/drivers/gpu/nova-core/gsp/sequencer.rs index 8d996e5e71c3..c414561576f8 100644 --- a/drivers/gpu/nova-core/gsp/sequencer.rs +++ b/drivers/gpu/nova-core/gsp/sequencer.rs @@ -71,6 +71,7 @@ pub(crate) enum GspSeqCmd { CoreReset, CoreStart, CoreWaitForHalt, + CoreResume, } impl GspSeqCmd { @@ -108,7 +109,7 @@ pub(crate) fn new(data: &[u8], dev: &device::Device) -> Result<(Self, usize)> { fw::SeqBufOpcode::CoreReset => (GspSeqCmd::CoreReset, opcode_size), fw::SeqBufOpcode::CoreStart => (GspSeqCmd::CoreStart, opcode_size), fw::SeqBufOpcode::CoreWaitForHalt => (GspSeqCmd::CoreWaitForHalt, opcode_size), - _ => return Err(EINVAL), + fw::SeqBufOpcode::CoreResume => (GspSeqCmd::CoreResume, opcode_size), }; if data.len() < size { @@ -121,7 +122,6 @@ pub(crate) fn new(data: &[u8], dev: &device::Device) -> Result<(Self, usize)> { } /// GSP Sequencer for executing firmware commands during boot. -#[expect(dead_code)] pub(crate) struct GspSequencer<'a> { /// Sequencer information with command data. seq_info: GspSequencerInfo, @@ -229,6 +229,46 @@ fn run(&self, seq: &GspSequencer<'_>) -> Result { seq.gsp_falcon.wait_till_halted(seq.bar)?; Ok(()) } + GspSeqCmd::CoreResume => { + // At this point, 'SEC2-RTOS' has been loaded into SEC2 by the sequencer + // but neither SEC2-RTOS nor GSP-RM is running yet. This part of the + // sequencer will start both. + + // Reset the GSP to prepare it for resuming. + seq.gsp_falcon.reset(seq.bar)?; + + // Write the libOS DMA handle to GSP mailboxes. + seq.gsp_falcon.write_mailboxes( + seq.bar, + Some(seq.libos_dma_handle as u32), + Some((seq.libos_dma_handle >> 32) as u32), + )?; + + // Start the SEC2 falcon which will trigger GSP-RM to resume on the GSP. + seq.sec2_falcon.start(seq.bar)?; + + // Poll until GSP-RM reload/resume has completed (up to 2 seconds). + seq.gsp_falcon + .check_reload_completed(seq.bar, Delta::from_secs(2))?; + + // Verify SEC2 completed successfully by checking its mailbox for errors. + let mbox0 = seq.sec2_falcon.read_mailbox0(seq.bar)?; + if mbox0 != 0 { + dev_err!(seq.dev, "Sequencer: sec2 errors: {:?}\n", mbox0); + return Err(EIO); + } + + // Configure GSP with the bootloader version. + seq.gsp_falcon + .write_os_version(seq.bar, seq.bootloader_app_version); + + // Verify the GSP's RISC-V core is active indicating successful GSP boot. + if !seq.gsp_falcon.is_riscv_active(seq.bar) { + dev_err!(seq.dev, "Sequencer: RISC-V core is not active\n"); + return Err(EIO); + } + Ok(()) + } } } } -- 2.34.1
