On Tue, Nov 18, 2025 at 3:53 AM Akhil P Oommen <[email protected]> wrote: > > AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides > in Raytracing related workloads. Add support for loading the AQE firmware > and initialize the necessary registers. > > Since AQE engine has dependency on preemption context records, expose > Raytracing support to userspace only when preemption is enabled.
I guess the plan is to expose MSM_PARAM_AQE later once preemption records are in place and for now just load the firmware to ensure that people have it? The interrupt error handling is still missing, but I guess that can be handled later if that's the plan. Connor > > Signed-off-by: Akhil P Oommen <[email protected]> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 22 ++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ > drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 3 +++ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > 4 files changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 810b64b909f5..9a643bcccdcf 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1118,6 +1118,23 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) > } > } > > + if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) { > + a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu, > + adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova); > + > + if (IS_ERR(a6xx_gpu->aqe_bo)) { > + int ret = PTR_ERR(a6xx_gpu->aqe_bo); > + > + a6xx_gpu->aqe_bo = NULL; > + DRM_DEV_ERROR(&gpu->pdev->dev, > + "Could not allocate AQE ucode: %d\n", ret); > + > + return ret; > + } > + > + msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw"); > + } > + > /* > * Expanded APRIV and targets that support WHERE_AM_I both need a > * privileged buffer to store the RPTR shadow > @@ -2400,6 +2417,11 @@ static void a6xx_destroy(struct msm_gpu *gpu) > drm_gem_object_put(a6xx_gpu->sqe_bo); > } > > + if (a6xx_gpu->aqe_bo) { > + msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm); > + drm_gem_object_put(a6xx_gpu->aqe_bo); > + } > + > if (a6xx_gpu->shadow_bo) { > msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->vm); > drm_gem_object_put(a6xx_gpu->shadow_bo); > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > index e6218b0b9732..3a054fcdeb4a 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > @@ -59,6 +59,8 @@ struct a6xx_gpu { > > struct drm_gem_object *sqe_bo; > uint64_t sqe_iova; > + struct drm_gem_object *aqe_bo; > + uint64_t aqe_iova; > > struct msm_ringbuffer *cur_ring; > struct msm_ringbuffer *next_ring; > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index c9cd7546024a..e011e80ceb50 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -627,6 +627,9 @@ static int hw_init(struct msm_gpu *gpu) > goto out; > > gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); > + if (a6xx_gpu->aqe_iova) > + gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, > a6xx_gpu->aqe_iova); > + > /* Set the ringbuffer address */ > gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); > gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index c496b63ffd41..0aca222c46bc 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -27,6 +27,7 @@ enum { > ADRENO_FW_PFP = 1, > ADRENO_FW_GMU = 1, /* a6xx */ > ADRENO_FW_GPMU = 2, > + ADRENO_FW_AQE = 3, > ADRENO_FW_MAX, > }; > > > -- > 2.51.0 >
