This is a respin of an old series [1] that aimed to add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. In this version, we have consolidated the previously separate series for DT and driver support, along with some significant rework.
Regarding A612 GPU, it falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU, a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement the IFPC feature. Unlike a full-fledged GMU, the RGMU does not support features such as clock control, resource voting via RPMh, HFI etc. Therefore, we require linux clock driver support similar to gmu-wrapper implementations to control gpu core clock and GX GDSC. In this series, the description of RGMU hardware in devicetree is more complete than in previous version. However, the RGMU core is not initialized from the driver as there is currently no need for it. We do perform a dummy load of RGMU firmware (now available in linux-firmware) to ensure that enabling RGMU core in the future won't break backward compatibility for users. Due to significant changes compared to the old series, all R-b tags have been dropped. Please review with fresh eyes. Last 3 patches are for Bjorn and the rest are for Rob Clark for pick up. [1] Driver: https://lore.kernel.org/lkml/[email protected]/ Devicetree: https://lore.kernel.org/lkml/fu4rayftf3i4arf6l6bzqyzsctomglhpiniljkeuj74ftvzlpo@vklca2giwjlw/ Signed-off-by: Akhil P Oommen <[email protected]> --- Changes in v3: - Rebased on top of next-20251121 tag - Drop a612 driver support patch as it got picked up - Rename rgmu.yaml -> qcom,adreno-rgmu.yaml (Krzysztof) - Remove reg-names property for rgmu node (Krzysztof) - Use 'gmu' instead of 'rgmu' as node name (Krzysztof) - Describe cx_mem and cx_dgc register ranges (Krzysztof) - A new patch to retrieve gmu core reg resource by id - Link to v2: https://lore.kernel.org/r/[email protected] Changes in v2: - Rebased on next-20251105 - Fix hwcg configuration (Dan) - Reuse a few gmu-wrapper routines (Konrad) - Split out rgmu dt schema (Krzysztof/Dmitry) - Fixes for GPU dt binding doc (Krzysztof) - Removed VDD_CX from rgmu dt node. Will post a separate series to address the gpucc changes (Konrad) - Fix the reg range size for adreno smmu node and reorder the properties (Konrad) - Link to v1: https://lore.kernel.org/r/[email protected] --- Akhil P Oommen (2): drm/msm/a6xx: Retrieve gmu core range by index dt-bindings: display/msm: gpu: Document A612 GPU Jie Zhang (3): dt-bindings: display/msm/rgmu: Document A612 RGMU arm64: dts: qcom: sm6150: Add gpu and rgmu nodes arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Qingqing Zhou (1): arm64: dts: qcom: sm6150: add the GPU SMMU node .../devicetree/bindings/display/msm/gpu.yaml | 24 +++- .../bindings/display/msm/qcom,adreno-rgmu.yaml | 126 ++++++++++++++++++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++ arch/arm64/boot/dts/qcom/talos.dtsi | 141 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 +- 6 files changed, 304 insertions(+), 10 deletions(-) --- base-commit: e93f8002e4d244f0642224635f457bc8b135c98b change-id: 20251015-qcs615-spin-2-ed45b0deb998 Best regards, -- Akhil P Oommen <[email protected]>
