On 11/27/2025 12:36 AM, Anna Maniscalco wrote: > Previously this register would become 0 after IFPC took place which > broke all usages of counters. > > Signed-off-by: Anna Maniscalco <[email protected]>
Reviewed-by: Akhil P Oommen <[email protected]> -Akhil > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 29107b362346..b731491dc522 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1392,6 +1392,7 @@ static const u32 a750_ifpc_reglist_regs[] = { > REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), > REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), > REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), > + REG_A6XX_RBBM_PERFCTR_CNTL, > REG_A6XX_TPL1_NC_MODE_CNTL, > REG_A6XX_SP_NC_MODE_CNTL, > REG_A6XX_CP_DBG_ECO_CNTL, > > --- > base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 > change-id: 20251126-ifpc_counters-e8d53fa3252e > > Best regards,
