On 11/27/25 12:46 AM, Anna Maniscalco wrote:
> GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe
> but it needs to be programmed for both.
>
> Program both pipes in hw_init and introducea separate reglist for it in
> order to add this register to the dynamic reglist which supports
> restoring registers per pipe.
>
> Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info")
> Signed-off-by: Anna Maniscalco <[email protected]>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 9 ++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 91
> +++++++++++++++++++++++++++++--
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 +++++
> 4 files changed, 109 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 29107b362346..c8d0b1d59b68 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
> REG_A6XX_UCHE_MODE_CNTL,
> REG_A6XX_RB_NC_MODE_CNTL,
> REG_A6XX_RB_CMP_DBG_ECO_CNTL,
> - REG_A7XX_GRAS_NC_MODE_CNTL,
> REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
> REG_A6XX_UCHE_GBIF_GX_CONFIG,
> REG_A6XX_UCHE_CLIENT_PF,
> @@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = {
>
> DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
>
> +static const struct adreno_reglist_pipe a750_reglist_pipe_regs[] = {
> + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
At a glance at kgsl, all gen7 GPUs that support concurrent binning (i.e.
not gen7_3_0/a710? and gen7_14_0/whatever that translates to) need this
Konrad
