Re: [PATCH v4 6/8] arm64: dts: qcom: talos: Add gpu and rgmu nodes

[Dmitry Baryshkov]

On Thu, Dec 04, 2025 at 06:51:58PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang <quic_ji...@quicinc.com>
> 
> Add gpu and rgmu nodes for Talos chipset.
> 
> Signed-off-by: Jie Zhang <quic_ji...@quicinc.com>
> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/talos.dtsi | 110 
> ++++++++++++++++++++++++++++++++++++
>  1 file changed, 110 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi 
> b/arch/arm64/boot/dts/qcom/talos.dtsi
> index 
> 743c840e496d70133bf82928e9e0c3da9653a5ee..effaff88df83d5e6a0aab45a2732a00cae11e83e
>  100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -647,6 +647,11 @@ rproc_adsp_mem: rproc-adsp@95900000 {
>                       reg = <0x0 0x95900000 0x0 0x1e00000>;
>                       no-map;
>               };
> +
> +             pil_gpu_mem: pil-gpu@97715000 {
> +                     reg = <0x0 0x97715000 0x0 0x2000>;
> +                     no-map;
> +             };
>       };
>  
>       soc: soc@0 {
> @@ -1826,6 +1831,111 @@ data-pins {
>                       };
>               };
>  
> +             gpu: gpu@5000000 {
> +                     compatible = "qcom,adreno-612.0", "qcom,adreno";
> +                     reg = <0x0 0x05000000 0x0 0x40000>,
> +                           <0x0 0x0509e000 0x0 0x1000>,
> +                           <0x0 0x05061000 0x0 0x800>;
> +                     reg-names = "kgsl_3d0_reg_memory",
> +                                 "cx_mem",
> +                                 "cx_dbgc";
> +
> +                     clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>;
> +                     clock-names = "core";
> +
> +                     interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                     interconnects = <&gem_noc MASTER_GFX3D 
> QCOM_ICC_TAG_ALWAYS
> +                                      &mc_virt SLAVE_EBI1 
> QCOM_ICC_TAG_ALWAYS>;
> +                     interconnect-names = "gfx-mem";
> +
> +                     iommus = <&adreno_smmu 0x0 0x401>;
> +
> +                     operating-points-v2 = <&gpu_opp_table>;
> +                     power-domains = <&rpmhpd RPMHPD_CX>;
> +
> +                     qcom,gmu = <&gmu>;
> +
> +                     #cooling-cells = <2>;
> +
> +                     status = "disabled";
> +
> +                     gpu_zap_shader: zap-shader {
> +                             memory-region = <&pil_gpu_mem>;
> +                     };
> +
> +                     gpu_opp_table: opp-table {
> +                             compatible = "operating-points-v2";
> +
> +                             opp-845000000 {
> +                                     opp-hz = /bits/ 64 <845000000>;
> +                                     required-opps = <&rpmhpd_opp_turbo>;
> +                                     opp-peak-kBps = <7050000>;

JFI, An ongoing discussion in v3 regarding OPP tables and speed bins.

> +                             };
> +

-- 
With best wishes
Dmitry