Re: [PATCH V1] accel/amdxdna: Enable hardware context priority

[Lizhi Hou]

Applied to drm-misc-next

On 12/17/25 09:59, Mario Limonciello wrote:

On 12/17/25 11:17 AM, Lizhi Hou wrote:

Newer firmware supports hardware context priority. Set the priority based

on application input.

Signed-off-by: Lizhi Hou <lizhi....@amd.com>

Reviewed-by: Mario Limonciello (AMD) <supe...@kernel.org>

This change itself is fine, but while reviewing it I did have a question to ask.

I notice that NPU2, NPU4, NPU5 and NPU6 all use npu4_fw_feature_table. Is this feature really present in F/W for NPU2 devices too?  Or it's really only NPU4 and later feature?

IE I just wonder if it's a non-obvious problem that npu2 device should have it's own fw feature table rather than re-use NPU4's. NPU1 has it's own feature table.

---
  drivers/accel/amdxdna/aie2_message.c  | 23 ++++++++++++++++++++++-
  drivers/accel/amdxdna/aie2_msg_priv.h |  5 +++++
  include/uapi/drm/amdxdna_accel.h      |  8 ++++++++
  3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c

index e77a353cadc5..051f4ceaabae 100644
--- a/drivers/accel/amdxdna/aie2_message.c
+++ b/drivers/accel/amdxdna/aie2_message.c

@@ -205,6 +205,27 @@ static int aie2_destroy_context_req(struct amdxdna_dev_hdl *ndev, u32 id)

        return ret;
  }
+
+static u32 aie2_get_context_priority(struct amdxdna_dev_hdl *ndev,
+                     struct amdxdna_hwctx *hwctx)
+{
+    if (!AIE2_FEATURE_ON(ndev, AIE2_PREEMPT))
+        return PRIORITY_HIGH;
+
+    switch (hwctx->qos.priority) {
+    case AMDXDNA_QOS_REALTIME_PRIORITY:
+        return PRIORITY_REALTIME;
+    case AMDXDNA_QOS_HIGH_PRIORITY:
+        return PRIORITY_HIGH;
+    case AMDXDNA_QOS_NORMAL_PRIORITY:
+        return PRIORITY_NORMAL;
+    case AMDXDNA_QOS_LOW_PRIORITY:
+        return PRIORITY_LOW;
+    default:
+        return PRIORITY_HIGH;
+    }
+}
+

  int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx)

  {
      DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT);

@@ -221,7 +242,7 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct

      req.num_unused_col = hwctx->num_unused_col;
      req.num_cq_pairs_requested = 1;
      req.pasid = hwctx->client->pasid;
-    req.context_priority = 2;
+    req.context_priority = aie2_get_context_priority(ndev, hwctx);
        ret = aie2_send_mgmt_msg_wait(ndev, &msg);
      if (ret)

diff --git a/drivers/accel/amdxdna/aie2_msg_priv.h b/drivers/accel/amdxdna/aie2_msg_priv.h

index cc912b7899ce..728ef56f7f0a 100644
--- a/drivers/accel/amdxdna/aie2_msg_priv.h
+++ b/drivers/accel/amdxdna/aie2_msg_priv.h
@@ -108,6 +108,11 @@ struct cq_pair {
      struct cq_info i2x_q;
  };
  +#define PRIORITY_REALTIME    1
+#define PRIORITY_HIGH        2
+#define PRIORITY_NORMAL        3
+#define PRIORITY_LOW        4
+
  struct create_ctx_req {
      __u32    aie_type;
      __u8    start_col;

diff --git a/include/uapi/drm/amdxdna_accel.h b/include/uapi/drm/amdxdna_accel.h

index 62c917fd4f7b..9c44db2b3dcd 100644
--- a/include/uapi/drm/amdxdna_accel.h
+++ b/include/uapi/drm/amdxdna_accel.h
@@ -19,6 +19,14 @@ extern "C" {
  #define AMDXDNA_INVALID_BO_HANDLE    0
  #define AMDXDNA_INVALID_FENCE_HANDLE    0
  +/*
+ * Define hardware context priority
+ */
+#define AMDXDNA_QOS_REALTIME_PRIORITY    0x100
+#define AMDXDNA_QOS_HIGH_PRIORITY    0x180
+#define AMDXDNA_QOS_NORMAL_PRIORITY    0x200
+#define AMDXDNA_QOS_LOW_PRIORITY    0x280
+
  enum amdxdna_device_type {
      AMDXDNA_DEV_TYPE_UNKNOWN = -1,
      AMDXDNA_DEV_TYPE_KMQ,