The AM62P and AM67A/J722S feature the same BXS-4 GPU as the J721S2. In theory, one have to just add the DT node. But it turns out, that the clock handling is not working. If I understood Nishan Menon correct, it is working on the J721S2 because there, the clock is shared, while on the AM62P the GPU has its own PLL. In the latter case, the driver will fail with a WARN() because the queried clock rate is zero due to a wrong cached value.
This was tested on the sa67 board which is based on the AM67A SoC. v2: - collect ACKs - rebase onto latest -next - new patch which enables 800MHz operation for the sa67 board v1: - https://lore.kernel.org/r/[email protected]/ - Don't set the clock to 800MHz in the soc dtsi. 800MHz is only possible if the core voltage is 0.85V. Just use the hardware default of 720MHz. A board device tree can set the 800MHz if applicable. Thanks Nishan. - Also add the new compatible to a conditional in the DT schema. Thanks Andrew. - Dropped the wrong of_clk_set_defaults() and instead disable caching of the clock rate. RFC: - https://lore.kernel.org/r/[email protected]/ Michael Walle (4): dt-bindings: gpu: img: Add AM62P SoC specific compatible clk: keystone: don't cache clock rate arm64: dts: ti: add GPU node arm64: dts: ti: sa67: set the GPU clock to 800MHz .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 2 ++ .../arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 11 +++++++++++ arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts | 6 ++++++ drivers/clk/keystone/sci-clk.c | 8 ++++++++ 4 files changed, 27 insertions(+) -- 2.47.3
