On 11/11/2025 10:21 AM, Damon Ding wrote:
In analogix_dp_link_start(), &link_train.training_lane[] is used to
set phy PE/VS configurations, and buf[] is initialized with the same
values to set DPCD DP_TRAINING_LANEx_SET.
It makes sense to reuse &link_train.training_lane[] to set DPCD
DP_TRAINING_LANEx_SET, which can remove the redundant assignments
and make codes more concise.
Signed-off-by: Damon Ding <[email protected]>
Tested-by: Marek Szyprowski <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
Changes in v2:
- Add Tested-by tag.
Changes in v3:
- Add Reviewed-by tag.
- Fix the spelling error 'consice' to 'concise'.
Gentle ping.
I just added tags in v2 and v3, and I also tried resend. The patch is
merely a pre-optimization work for the following patch series:
https://lore.kernel.org/all/[email protected]/
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 6ec3d811b5f0..1e834d3656c1 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -281,12 +281,8 @@ static int analogix_dp_link_start(struct
analogix_dp_device *dp)
if (retval < 0)
return retval;
- for (lane = 0; lane < lane_count; lane++)
- buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
- DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
-
- retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
- lane_count);
+ retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
+ dp->link_train.training_lane, lane_count);
if (retval < 0)
return retval;
