On Mon, Dec 29, 2025 at 12:39:13PM +0100, Marijn Suijten wrote:
> On 2025-12-28 05:57:12, Dmitry Baryshkov wrote:
> > Since DPU 8.x Watchdog timer settings were moved from the TOP to the
> > INTF block. Support programming the timer in the INTF block. Fixes tag
> > points to the commit which removed register access to thos registers on
>
> thos -> those
>
> > DPU 8.x+ (and which also should have added proper support for WD timer
> > on those devices).
>
> Right, yes. Commit 2f69e5458447 ("drm/msm/dpu: skip watchdog timer
> programming
> through TOP on >= SM8450") was already a fixup of that (though marked as
> fixing
> the followup commit 100d7ef ("drm/msm/dpu: add support for SM8450") for being
> the first to use the new DPU_MDP_PERIPH_0_REMOVED flag).
>
> >
> > Fixes: 43e3293fc614 ("drm/msm/dpu: add support for MDP_TOP blackhole")
> > Signed-off-by: Dmitry Baryshkov <[email protected]>
>
> Reviewed-by: Marijn Suijten <[email protected]>
>
> ...
> > @@ -791,7 +791,7 @@ static void _dpu_encoder_update_vsync_source(struct
> > dpu_encoder_virt *dpu_enc,
> >
> > if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
> > phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
> > -
> > vsync_cfg.vsync_source);
> > + &vsync_cfg);
>
> In some way this makes me wonder if we simply need another struct, in favour
> of not missing fields that are never / not-yet read, although resulting in
> more
> clutter.
>
> (Just a nit / question, not a request)
>
> ...
> > + if (cfg->vsync_source == DPU_VSYNC_SOURCE_WD_TIMER_0) {
> > + u32 reg;
> > +
> > + DPU_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE,
> > + CALCULATE_WD_LOAD_VALUE(cfg->frame_rate));
> > +
> > + DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */
> > + reg = DPU_REG_READ(c, INTF_WD_TIMER_0_CTL2);
> > + reg |= BIT(8); /* enable heartbeat timer */
> > + reg |= BIT(0); /* enable WD timer */
>
> My downstream also sets BIT(1) for "select default 16 clock ticks":
>
> https://github.com/sonyxperiadev/kernel-techpack-display-driver/blob/61a727e1ce1fda617a73793b2cbb76b5ca846ea2/msm/sde/sde_hw_intf.c#L511
>
> Although it doesn't read back the current register value. Do we need that; or
> maybe you are inferring this "missing" BIT(1) via this readback?
>
> After all downstream removed the readback exactly in favour of setting BIT(1)
> though because of a "default value change" since MDSS 9.x.x:
Ack, thanks for the note.
>
> https://github.com/sonyxperiadev/kernel-techpack-display-driver/commit/e55c68138b04770d51067c158f92de526e0c926e
>
> - Marijn
--
With best wishes
Dmitry
