The minimum alignment for both the header and data buffers in the AFBC format for Mali GPUs with archicture version 6 and higher (which includes MT8195's G57 (v9)) is 128, not 1024 as the MediaTek DRM driver currently defines.
Since Mesa defines it as the correct value of 128 [1], when displaying AFBC buffers, some resolutions will cause the OVL component to be configured by the driver with a data address that is different from the address that actually contains the data as set by Mesa, resulting in corrupted output on display. Fix the AFBC alignment definition for the MediaTek DRM driver. [1] https://gitlab.freedesktop.org/mesa/mesa/-/blob/3848a080534a17ca075e9e95dd3a14abb80139aa/src/panfrost/lib/pan_afbc.h#L364 Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver") Signed-off-by: Nícolas F. R. A. Prado <[email protected]> --- drivers/gpu/drm/mediatek/mtk_plane.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediatek/mtk_plane.h index 95c5fa5295d8..46be4454bc92 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_plane.h @@ -13,7 +13,7 @@ #define AFBC_DATA_BLOCK_WIDTH 32 #define AFBC_DATA_BLOCK_HEIGHT 8 #define AFBC_HEADER_BLOCK_SIZE 16 -#define AFBC_HEADER_ALIGNMENT 1024 +#define AFBC_HEADER_ALIGNMENT 128 struct mtk_plane_pending_state { bool config; -- 2.51.0
