On 11/4/25 6:25 AM, Liu Ying wrote:

Hello Liu,

sorry for my late reply.

+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -61,24 +61,16 @@ enum fsl_ldb_devtype {
    };
      struct fsl_ldb_devdata {
-    u32 ldb_ctrl;
-    u32 lvds_ctrl;
        bool lvds_en_bit;
        bool single_ctrl_reg;

single_ctrl_reg can be dropped then, as it can be expressed by failing to
get the second register.

Furthermore, with this done, lvds_en_bit is the only member left and hence
struct fsl_ldb_devdata can also be dropped, as IIRC there is no need to
use a structure for device data with only a flag.
I plan to add more bits into the driver match data when adding the MX95,
so I would like to retain these instead of removing them and the adding
them back.

i.MX95 LDB supports two LVDS channels.  Two DRM bridges are needed in single
or separate LDB mode, while one DRM bridge is needed in split LDB mode.

What do you refer to by "split LDB mode" , some interleaving or some such
thing ?

I mean "Split Channel DI0" and "Split Channel DI1" use cases in the below
table in i.MX95 TRM.

+------------------------------------------------------------+
|Table: Channel Mapping                                      |
|------------------------------------------------------------|
|Use Case           |  LVDS Channel 0   |  LVDS Channel 1    |
|------------------------------------------------------------|
|Single Channel DI0 | DI0               | Disabled           |
|------------------------------------------------------------|
|Single Channel DI1 | Disabled          | DI1                |
|------------------------------------------------------------|
|Separate Channels  | DI0               | DI1                |
|------------------------------------------------------------|
|Dual Channels DI0  | DI0               | DI0                |
|------------------------------------------------------------|
|Dual Channels DI1  | DI1               | DI1                |
|------------------------------------------------------------|
|Split Channel DI0  | DI0 (first pixel) | DI0 (second pixel) |
|------------------------------------------------------------|
|Split Channel DI1  | DI1 (first pixel) | DI1 (second pixel) |
+------------------------------------------------------------+
So yes, split mode is effectively interleaving. But that should only be a matter of syscon configuration.

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