On Thu, Jan 08, 2026 at 04:56:57PM +0800, yuanjie yang wrote:
> From: Yuanjie Yang <[email protected]>
>
> Add support for Kaanapali platform SSPP sub-blocks, which
> introduce structural changes including register additions,
> removals, and relocations. Add the new common and rectangle
> blocks, and update register definitions and handling to
> ensure compatibility with DPU v13.0.
>
> Co-developed-by: Yongxing Mou <[email protected]>
> Signed-off-by: Yongxing Mou <[email protected]>
> Signed-off-by: Yuanjie Yang <[email protected]>
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 14 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> 7 files changed, 371 insertions(+), 4 deletions(-)
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
>
> +
> +void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
> + unsigned long features, const struct dpu_mdss_version
> *mdss_rev)
> +{
> + c->ops.setup_format = dpu_hw_sspp_setup_format_v13;
> + c->ops.setup_rects = dpu_hw_sspp_setup_rects_v13;
Wrong indentation.
> + c->ops.setup_sourceaddress =
> dpu_hw_sspp_setup_sourceaddress_v13;
> + c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill_v13;
> + c->ops.setup_pe = dpu_hw_sspp_setup_pe_config_v13;
> +
> /* QOS_QOS_CTRL */
> #define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0)
> #define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)
> @@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c,
> u32 offset,
> cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
> }
>
> +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
> + const struct dpu_hw_qos_cfg *cfg)
Will it be shared with other blocks (DS, WB)?
> +{
> + DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);
> + DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);
> + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);
> + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);
> + DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,
> + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
> +}
> +
> /*
> * note: Aside from encoders, input_sel should be set to 0x0 by default
> */
--
With best wishes
Dmitry
