Hi Tommaso,
On Wed, 26 Nov 2025 at 15:09, Tommaso Merciai
<[email protected]> wrote:
> Add definitions for DSI clocks and resets on the R9A09G047 cpg driver
> to enable proper initialization and control of the DSI hardware.
>
> Signed-off-by: Tommaso Merciai <[email protected]>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -486,6 +486,18 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[]
> __initconst = {
> BUS_MSTOP(9, BIT(4))),
> DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6,
> 20,
> BUS_MSTOP(9, BIT(4))),
> + DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
> + BUS_MSTOP(9, BIT(15) |
> BIT(14))),
> + DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9,
> 7, 9,
> + BUS_MSTOP(9, BIT(15) |
> BIT(14))),
> + DEF_MOD("dsi_0_vclk1", CLK_SMUX2_DSI0_CLK, 14, 10,
> 7, 10,
> + BUS_MSTOP(9, BIT(15) |
> BIT(14))),
> + DEF_MOD("dsi_0_vclk2", CLK_SMUX2_DSI1_CLK, 25, 0,
> 10, 21,
> + BUS_MSTOP(9, BIT(15) |
> BIT(14))),
Please move this below, to preserve sort order (by _onindex/_onbit)
> + DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK, 14, 11, 7,
> 11,
> + BUS_MSTOP(9, BIT(15) |
> BIT(14))),
> + DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
> + BUS_MSTOP(9, BIT(15) |
> BIT(14))),
> DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
> BUS_MSTOP(3, BIT(4))),
> DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1,
> 7, 17,
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
