On Mon, Jan 12, 2026 at 03:25:05PM +0800, Xilin Wu wrote: > On 1/12/2026 11:11 AM, Dmitry Baryshkov wrote: > > From: Jessica Zhang <[email protected]> > > > > LM block doesn't have a hardware buffer (unlike PINGPONG and DSC > > encoders). As such, don't use ephemeral max_mixer_width and > > MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC > > buffer widths. > > > > While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0, > > there is some additional logic that needs to be added to the resource > > manager to specifically try and reserve PINGPONG_0 for modes that are > > greater than 5k. > > > > Signed-off-by: Jessica Zhang <[email protected]> > > Tested-by: Xilin Wu <[email protected]> # qcs6490-radxa-dragon-q6a > > [DB: reworked to drop catalog changes, updated commit message] > > Signed-off-by: Dmitry Baryshkov <[email protected]> > > Sorry for the late reply, my colleagues are still testing the new series on > qcs6490. > > However, this completely breaks 4K 120Hz display on SC8280XP CRD, which was > previously functional (albeit with the clock check bypassed [1]). The > display now shows a solid blue screen. Kernel logs indicate that only one > layer mixer is being used, instead of the two that were used previously.
Could you please post debugfs/dri/0/state and debugfs/dri/0/debug/core_perf/*? > > [1] > https://lore.kernel.org/all/[email protected]/ > > -- > Best regards, > Xilin Wu <[email protected]> -- With best wishes Dmitry
