On 1/13/2026 7:47 AM, Marek Vasut wrote: > [You don't often get email from [email protected]. Learn why > this is important at https://aka.ms/LearnAboutSenderIdentification ] > > Caution: This is an external email. Please take care when clicking links or > opening attachments. When in doubt, report the message using the 'Report this > email' button > > > Parse the data lane count out of DT. Limit the supported data lanes > to 1..4 which is the maximum available DSI pairs on the connector of > any known panels which may use this bridge. Internally, this bridge > is an ChipOne ICN6211 which loads its register configuration from a > dedicated storage and its I2C does not seem to be accessible. The > ICN6211 also supports up to 4 DSI lanes, so this is a hard limit. > > To avoid any breakage on old DTs where the parsing of data lanes from > DT may fail, fall back to the original hard-coded value of 2 lanes and > warn user. > > The lane configuration is preconfigured in the bridge for each of the > WaveShare panels. The 13.3" DSI panel works with 4-lane configuration, > others seem to use 2-lane configuration. This is a hardware property, > so the actual count should come from DT. > > Hi Marek,
I don't have 4 lanes waveshare panel on my hands. Have you tested with the 4-lane panel already? Regards, Joseph
