On Mon, 15 Dec 2025 17:14:50 +0000
Lukas Zapolskas <[email protected]> wrote:
> +/**
> + * PANTHOR_PERF_EM_BITS - Number of bits in a user-facing enable mask. This
> must correspond
> + * to the maximum number of counters available for
> selection on the newest
> + * Mali GPUs (128 as of the Mali-Gx15).
This statement worries me a bit. It seems to imply that we might have
more than 128 counters per block at some point, and the way the uAPI is
designed, it's going to be annoying to extend. Maybe we should come up
with an approach that would account for this from the start, like:
- Moving drm_panthor_perf_block_header::enable_mask in its own
drm_panthor_perf_block_enable_header_mask whose size can be
determined from perf_info::counters_per_block
- having the enable mask settings passed through an array of
struct drm_panthor_perf_enable_counter_section looking something like
that:
/** @struct drm_panthor_perf_enable_counter_section - Describes a counter
section to enable */
struct drm_panthor_perf_enable_counter_section {
/** @block_type: block type this section refers to */
__u8 block_type;
/**
* @block_counter_offset: counter offset in the block type
*
* This must bit 64 aligned, and block_counter_offset + 64 must be
* <= drm_panthor_perf_info::counters_per_block
*/
__u8 block_counter_offset;
/** @padding: MBZ. */
__u16 padding;
/**
* @enable_mask: enable mask to set for this portion of the counter
block.
*
* The targeted counters are [@block_counter_offset,
@block_counter_offset + 63].
*/
__u64 enable_mask;
};
struct drm_panthor_perf_block_setup {
...
__u64 sample_freq_ns;
/// All xxx_enable[2] fields are replaced by the following array.
/** @enable_sections: Sections of the counter blocks to enable. */
struct drm_panthor_obj_array enable_sections;
}
> + */
> +#define PANTHOR_PERF_EM_BITS (BITS_PER_TYPE(u64) * 2)
