Some HDMI 2.0 monitors require additional time to process SCDC configuration before PHY initialization begins. Without this delay, certain monitors (e.g., Cisco Desk Pro) fail to detect the scrambled signal at 4K@60Hz and report format detection errors, despite successful SCDC I2C transactions.
Testing with multiple delay positions in the modeset sequence revealed that the timing is not tied to any specific PHY/DDI operation. The monitor simply needs ~150ms after SCDC configuration to prepare its scrambling detection logic before subsequent operations begin. The delay is placed immediately after intel_hdmi_handle_sink_scrambling() to make the code intent clear: we're giving the monitor time to process SCDC configuration. This placement also allows subsequent PHY operations to benefit from the monitor's preparation time. The 150ms value was determined through systematic testing and aligns with HDMI 2.0 spec section 10.4.1.7, which mentions monitors can disable scrambling if they don't detect a scrambled signal within 100ms. Some monitors appear to need additional margin for SCDC processing. Testing methodology: Created 4 test patches, progressively moving the delay earlier in the intel_ddi_enable_hdmi() sequence: - Test 1: Before intel_ddi_buf_enable() (line ~3504) - SUCCESS - Test 2: Before intel_ddi_power_up_lanes() (line ~3466) - SUCCESS - Test 3: After set_signal_levels() (line ~3429) - SUCCESS - Test 4: After hsw_prepare_hdmi_ddi_buffers() (line ~3424) - SUCCESS All tests succeeded, confirming the delay works at any position after SCDC configuration. The earliest position (immediately after SCDC config) was chosen for code clarity and maintainability. Changes in v2: - Moved delay to immediately after SCDC configuration (was at end of modeset sequence in v1) - Added detailed testing results showing delay works at any position - Improved comment explaining the root cause and placement rationale - Based on feedback from Ville Syrjälä suggesting to identify the exact operation requiring the delay Tested-by: Jerome Tollet <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Jerome Tollet <[email protected]> --- drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3de3e9167..328884efa 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3419,6 +3419,20 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", connector->base.id, connector->name); + /* + * HDMI 2.0 spec section 10.4.1.7: Some monitors need time to process + * the SCDC configuration before PHY initialization begins. Testing + * shows the delay can be placed anywhere in the modeset sequence after + * SCDC config, but placing it here (immediately after) makes the code + * intent clear and allows subsequent PHY operations to benefit from + * the monitor preparation time. + * + * Without this delay, certain monitors (e.g., Cisco Desk Pro) fail to + * detect the scrambled signal and report format detection errors despite + * proper SCDC configuration. + */ + if (crtc_state->hdmi_scrambling) + msleep(150); if (has_buf_trans_select(display)) hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); -- 2.43.0
