The AM62L DSS [1] support incorrectly used the same register and clock constraints as AM65x, but AM62L has a single video port.
Fix this by adding conditional constraints that properly define the register regions and clocks for AM62L DSS (single video port) versus other AM65x variants (dual video port). [1]: Section 12.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS") Cc: [email protected] Signed-off-by: Swamil Jain <[email protected]> --- Changelog: v1->v2: - Remove oneOf from top level constraints, it makes bindings redundant - Remove minItems from top level constraints - "dma-coherent" property shouldn't be changed in v1 itself - Add description for reg-names, clock and clock-names - Add constraints specific to AM62L and for other SoCs within allOf check Link to v1: https://lore.kernel.org/all/[email protected]/ --- .../bindings/display/ti/ti,am65x-dss.yaml | 93 +++++++++++++------ 1 file changed, 67 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 38fcee91211e..dbc9d754cf9e 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -36,38 +36,18 @@ properties: reg: description: Addresses to each DSS memory region described in the SoC's TRM. - items: - - description: common DSS register area - - description: VIDL1 light video plane - - description: VID video plane - - description: OVR1 overlay manager for vp1 - - description: OVR2 overlay manager for vp2 - - description: VP1 video port 1 - - description: VP2 video port 2 - - description: common1 DSS register area reg-names: - items: - - const: common - - const: vidl1 - - const: vid - - const: ovr1 - - const: ovr2 - - const: vp1 - - const: vp2 - - const: common1 + description: + Names for each memory region described in the reg property. clocks: - items: - - description: fck DSS functional clock - - description: vp1 Video Port 1 pixel clock - - description: vp2 Video Port 2 pixel clock + description: + Clocks used by the DSS. The number and order depends on the SoC variant. clock-names: - items: - - const: fck - - const: vp1 - - const: vp2 + description: + Names for each clock described in the clocks property. The number and order depends on the SoC variant. assigned-clocks: minItems: 1 @@ -195,6 +175,67 @@ allOf: port@0: properties: endpoint@1: false + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + clock-names: + items: + - const: fck + - const: vp1 + clocks: + items: + - description: fck DSS functional clock + - description: vp1 Video Port 1 pixel clock + reg: + items: + - description: common DSS register area + - description: VIDL1 light video plane + - description: OVR1 overlay manager for vp1 + - description: VP1 video port 1 + - description: common1 DSS register area + reg-names: + items: + - const: common + - const: vidl1 + - const: ovr1 + - const: vp1 + - const: common1 + else: + properties: + clock-names: + items: + - const: fck + - const: vp1 + - const: vp2 + clocks: + items: + - description: fck DSS functional clock + - description: vp1 Video Port 1 pixel clock + - description: vp2 Video Port 2 pixel clock + reg: + items: + - description: common DSS register area + - description: VIDL1 light video plane + - description: VID video plane + - description: OVR1 overlay manager for vp1 + - description: OVR2 overlay manager for vp2 + - description: VP1 video port 1 + - description: VP2 video port 2 + - description: common1 DSS register area + reg-names: + items: + - const: common + - const: vidl1 + - const: vid + - const: ovr1 + - const: ovr2 + - const: vp1 + - const: vp2 + - const: common1 required: - compatible
