Increase maximum VI clock frequency to 450MHz to allow correct work with high resolution camera sensors.
Tested-by: Luca Ceresoli <[email protected]> # tegra20, parallel camera Signed-off-by: Svyatoslav Ryhel <[email protected]> Reviewed-by: Mikko Perttunen <[email protected]> --- drivers/staging/media/tegra-video/tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c index 7ceefd920cd6..bf8755698610 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -598,7 +598,7 @@ const struct tegra_vi_soc tegra20_vi_soc = { .ops = &tegra20_vi_ops, .hw_revision = 1, .vi_max_channels = 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */ - .vi_max_clk_hz = 150000000, + .vi_max_clk_hz = 450000000, .has_h_v_flip = true, }; -- 2.51.0
