From: Boris Brezillon <[email protected]> Add register definitions and constants for managing MMU address space, including: - Address space translation configuration (page table format, attributes) - Memory attributes (cacheability, shareability) - Address space commands (update, lock, flush) - AsRegister helper for per-AS register access
These will be used by the MMU/VM manager to configure page tables and control address space operations. Signed-off-by: Boris Brezillon <[email protected]> Co-developed-by: Deborah Brouwer <[email protected]> Signed-off-by: Deborah Brouwer <[email protected]> --- drivers/gpu/drm/tyr/regs.rs | 101 +++++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs index 611870c2e6af..9cb7ab0c806a 100644 --- a/drivers/gpu/drm/tyr/regs.rs +++ b/drivers/gpu/drm/tyr/regs.rs @@ -8,7 +8,10 @@ #![allow(dead_code)] use kernel::{ - bits::bit_u32, + bits::{ + bit_u32, + bit_u64, // + }, device::{ Bound, Device, // @@ -111,3 +114,99 @@ pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u3 pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register; pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register; pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register; + +pub(crate) const AS_TRANSCFG_ADRMODE_UNMAPPED: u64 = bit_u64(0); +pub(crate) const AS_TRANSCFG_ADRMODE_AARCH64_4K: u64 = bit_u64(2) | bit_u64(1); +pub(crate) const AS_TRANSCFG_PTW_MEMATTR_WB: u64 = bit_u64(25); +pub(crate) const AS_TRANSCFG_PTW_RA: u64 = bit_u64(30); + +pub(crate) const fn as_transcfg_ina_bits(x: u64) -> u64 { + x << 6 +} + +pub(crate) const AS_MEMATTR_AARCH64_SH_MIDGARD_INNER: u32 = 0 << 4; +pub(crate) const AS_MEMATTR_AARCH64_INNER_OUTER_NC: u32 = 1 << 6; +pub(crate) const AS_MEMATTR_AARCH64_INNER_OUTER_WB: u32 = 2 << 6; + +pub(crate) fn as_memattr_aarch64_inner_alloc_expl(w: bool, r: bool) -> u32 { + (3 << 2) | (u32::from(w)) | ((u32::from(r)) << 1) +} + +pub(crate) const AS_COMMAND_UPDATE: u32 = 1; +pub(crate) const AS_COMMAND_LOCK: u32 = 2; +pub(crate) const AS_COMMAND_FLUSH_PT: u32 = 4; +pub(crate) const AS_COMMAND_FLUSH_MEM: u32 = 5; + +pub(crate) const AS_STATUS_ACTIVE: u32 = bit_u32(0); + +pub(crate) const AS_LOCK_REGION_MIN_SIZE: u32 = bit_u32(15); + +/// Maximum number of hardware address space slots. +/// The actual number of slots available is usually much lower. +pub(crate) const MAX_AS_REGISTERS: usize = 32; + +const MMU_BASE: usize = 0x2400; +const MMU_AS_SHIFT: usize = 6; + +const fn mmu_as(as_nr: usize) -> usize { + MMU_BASE + (as_nr << MMU_AS_SHIFT) +} + +pub(crate) struct AsRegister(usize); + +impl AsRegister { + fn new(as_nr: usize, offset: usize) -> Result<Self> { + Ok(AsRegister(mmu_as(as_nr) + offset)) + } + + #[inline] + pub(crate) fn read(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<u32> { + let value = (*iomem).access(dev)?.try_read32(self.0)?; + Ok(value) + } + + #[inline] + pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u32) -> Result { + (*iomem).access(dev)?.try_write32(value, self.0)?; + Ok(()) + } +} + +pub(crate) fn as_transtab_lo(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x0) +} + +pub(crate) fn as_transtab_hi(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x4) +} + +pub(crate) fn as_memattr_lo(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x8) +} + +pub(crate) fn as_memattr_hi(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0xc) +} + +pub(crate) fn as_lockaddr_lo(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x10) +} + +pub(crate) fn as_lockaddr_hi(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x14) +} + +pub(crate) fn as_command(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x18) +} + +pub(crate) fn as_status(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x28) +} + +pub(crate) fn as_transcfg_lo(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x30) +} +pub(crate) fn as_transcfg_hi(as_nr: usize) -> Result<AsRegister> { + AsRegister::new(as_nr, 0x34) +} -- 2.52.0
