Read GPU_TEXTURE_FEATURES registers 1 through 3 in addition to register 0, matching the C Panthor driver's behavior. Previously only texture_features[0] was read from hardware while [1], [2], and [3] were hardcoded to zero.
Signed-off-by: Artem Lytkin <[email protected]> --- drivers/gpu/drm/tyr/gpu.rs | 10 +++++++--- drivers/gpu/drm/tyr/regs.rs | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tyr/gpu.rs b/drivers/gpu/drm/tyr/gpu.rs index 6c582910dd5d..480cad86a602 100644 --- a/drivers/gpu/drm/tyr/gpu.rs +++ b/drivers/gpu/drm/tyr/gpu.rs @@ -58,7 +58,12 @@ pub(crate) fn new(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<Self> { let thread_max_barrier_size = regs::GPU_THREAD_MAX_BARRIER_SIZE.read(dev, iomem)?; let coherency_features = regs::GPU_COHERENCY_FEATURES.read(dev, iomem)?; - let texture_features = regs::GPU_TEXTURE_FEATURES0.read(dev, iomem)?; + let texture_features = [ + regs::GPU_TEXTURE_FEATURES0.read(dev, iomem)?, + regs::GPU_TEXTURE_FEATURES1.read(dev, iomem)?, + regs::GPU_TEXTURE_FEATURES2.read(dev, iomem)?, + regs::GPU_TEXTURE_FEATURES3.read(dev, iomem)?, + ]; let as_present = regs::GPU_AS_PRESENT.read(dev, iomem)?; @@ -86,8 +91,7 @@ pub(crate) fn new(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<Self> { thread_max_workgroup_size, thread_max_barrier_size, coherency_features, - // TODO: Add texture_features_{1,2,3}. - texture_features: [texture_features, 0, 0, 0], + texture_features, as_present, pad0: 0, shader_present, diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs index f46933aaa221..b51e09fe2fc4 100644 --- a/drivers/gpu/drm/tyr/regs.rs +++ b/drivers/gpu/drm/tyr/regs.rs @@ -67,6 +67,9 @@ pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u3 pub(crate) const GPU_THREAD_MAX_WORKGROUP_SIZE: Register<0xa4> = Register; pub(crate) const GPU_THREAD_MAX_BARRIER_SIZE: Register<0xa8> = Register; pub(crate) const GPU_TEXTURE_FEATURES0: Register<0xb0> = Register; +pub(crate) const GPU_TEXTURE_FEATURES1: Register<0xb4> = Register; +pub(crate) const GPU_TEXTURE_FEATURES2: Register<0xb8> = Register; +pub(crate) const GPU_TEXTURE_FEATURES3: Register<0xbc> = Register; pub(crate) const GPU_SHADER_PRESENT_LO: Register<0x100> = Register; pub(crate) const GPU_SHADER_PRESENT_HI: Register<0x104> = Register; pub(crate) const GPU_TILER_PRESENT_LO: Register<0x110> = Register; -- 2.43.0
