On Tue, Mar 03, 2026 at 11:03:11AM +0200, Abel Vesa wrote: > The Glymur platform has four DisplayPort controllers. The hardware > supports four streams (MST) per controller. However, on Glymur the first > three controllers only have two streams wired to the display subsystem, > while the fourth controller operates in single-stream mode. > > Add a dedicated clause for the Glymur compatible to require the register > ranges for all four stream blocks, while allowing either one pixel clock > (for the single-stream controller) or two pixel clocks (for the remaining > controllers). > > Update the Glymur MDSS schema example by adding the missing p2, p3, > mst2link and mst3link register blocks. Without these, the bindings > validation fails. Also replace the made-up register addresses with the > actual addresses from the first controller to match the SoC devicetree > description. > > Cc: [email protected] # v6.19 > Fixes: 8f63bf908213 ("dt-bindings: display: msm: Document the Glymur > DiplayPort controller") > Fixes: 1aee577bbc60 ("dt-bindings: display: msm: Document the Glymur Mobile > Display SubSystem") > Signed-off-by: Abel Vesa <[email protected]> > --- > Did not pick up Dmitry's R-b tag as patches have been squashed > and commit message re-worded.
Reviewed-by: Krzysztof Kozlowski <[email protected]> Best regards, Krzysztof
