[PATCH 05/24] drm/msm/adreno: use qcom_ubwc_version_tag() helper

[Dmitry Baryshkov]

Use new helper defined to program UBWC version to the hardware.

Reviewed-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a8xx_gpu.c |  8 +++-----
 drivers/gpu/drm/msm/msm_mdss.c        | 16 +---------------
 2 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index b1887e0cf698..6dc1d81fcaeb 100644
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -272,35 +272,33 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu)
        bool rgb565_predicator = false, amsbc = false;
        bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
        u32 ubwc_version = cfg->ubwc_enc_version;
-       u32 hbb, hbb_hi, hbb_lo, mode = 1;
+       u32 hbb, hbb_hi, hbb_lo, mode;
        u8 uavflagprd_inv = 2;
 
        switch (ubwc_version) {
        case UBWC_6_0:
                yuvnotcomptofc = true;
-               mode = 5;
                break;
        case UBWC_5_0:
                amsbc = true;
                rgb565_predicator = true;
-               mode = 4;
                break;
        case UBWC_4_0:
                amsbc = true;
                rgb565_predicator = true;
                fp16compoptdis = true;
                rgba8888_lossless = true;
-               mode = 2;
                break;
        case UBWC_3_0:
                amsbc = true;
-               mode = 1;
                break;
        default:
                dev_err(&gpu->pdev->dev, "Unknown UBWC version: 0x%x\n", 
ubwc_version);
                break;
        }
 
+       mode = qcom_ubwc_version_tag(cfg);
+
        /*
         * We subtract 13 from the highest bank bit (13 is the minimum value
         * allowed by hw) and write the lowest two bits of the remaining value
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 9f81f43283b9..798a23fbc906 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -204,7 +204,7 @@ static void msm_mdss_setup_ubwc_v6(struct msm_mdss 
*msm_mdss)
        const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
        u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
                    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 
13);
-       u32 ver, prediction_mode;
+       u32 prediction_mode;
 
        if (data->ubwc_bank_spread)
                value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
@@ -222,20 +222,6 @@ static void msm_mdss_setup_ubwc_v6(struct msm_mdss 
*msm_mdss)
        else
                prediction_mode = 1;
 
-       if (data->ubwc_enc_version >= UBWC_6_0)
-               ver = 5;
-       else if (data->ubwc_enc_version >= UBWC_5_0)
-               ver = 4;
-       else if (data->ubwc_enc_version >= UBWC_4_3)
-               ver = 3;
-       else if (data->ubwc_enc_version >= UBWC_4_0)
-               ver = 2;
-       else if (data->ubwc_enc_version >= UBWC_3_0)
-               ver = 1;
-       else /* UBWC 1.0 and 2.0 */
-               ver = 0;
-
-       writel_relaxed(ver, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
        writel_relaxed(prediction_mode, msm_mdss->mmio + 
REG_MDSS_UBWC_PREDICTION_MODE);
 }
 

-- 
2.47.3