On Sun, Mar 22, 2026 at 02:31:13PM +0000, Alexander Koskovich wrote:
> Derive INTF data_width from dce_bytes_per_line rather than
> timing->width when DSC is enabled. Use DIV_ROUND_UP to avoid
> rounding errors.
>
> Signed-off-by: Alexander Koskovich <[email protected]>
> ---
> This patch changes the data_width calculation to match downstream,
> and avoids needing to change the divisor for timing->width to /24.
>
> However I am not sure if this is a correct approach, but at least
> with this I get the same values for data_width as downstream now:
>
> data_width w/ no widebus
> before: 288
> after: 360
>
> data_with w/ widebus
> before: 144
> after: 180
>
> This was tested with the BOE BF068MWM-TD0 on the Nothing Phone (3a),
> it would be greatly appreciated if someone from QCOM could weigh in
> on if this is a correct approach.
>
> Tested with kmscube and getting 120FPS, also note that this was
> tested with a few other changes:
>
> (drm/msm/dsi: fix hdisplay calculation when programming dsi registers)
This is a part of msm-fixes
> (drm/msm/dsi: fix pclk rate calculation for bonded dsi)
This is a part of msm-fixes
> (drm/msm/dsi: fix bits_per_pclk)
> (drm/msm/dsi: fix hdisplay calculation for CMD mode panel)
Okay, let's pick these two. I assume we've had enough of testing. I hope
Marijn can also r-b those.
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 23
> +++++++++++++++++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 +
> 3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 0ba777bda253..ba810f26ea30 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -10,6 +10,7 @@
> #include "dpu_formats.h"
> #include "dpu_trace.h"
> #include "disp/msm_disp_snapshot.h"
> +#include "msm_dsc_helper.h"
>
> #include <drm/display/drm_dsc_helper.h>
> #include <drm/drm_managed.h>
> @@ -136,6 +137,7 @@ static void drm_mode_to_intf_timing_params(
> timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
> (dsc->bits_per_component * 3);
> timing->xres = timing->width;
> + timing->dce_bytes_per_line = msm_dsc_get_bytes_per_line(dsc);
> }
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 7e620f590984..de6b5b0f70c4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -173,13 +173,26 @@ static void dpu_hw_intf_setup_timing_engine(struct
> dpu_hw_intf *intf,
> data_width = p->width;
>
> /*
> - * If widebus is enabled, data is valid for only half the active window
> - * since the data rate is doubled in this mode. But for the compression
> - * mode in DP case, the p->width is already adjusted in
> - * drm_mode_to_intf_timing_params()
Please keep the DP comment. We need to fix the assymmetry between DSI
and DP, but that needs DP DSC support first.
With that in place, the patch LGTM.
> + * If widebus is disabled:
> + * For uncompressed stream, the data is valid for the entire active
> + * window period.
> + * For compressed stream, data is valid for a shorter time period
> + * inside the active window depending on the compression ratio.
> + *
> + * If widebus is enabled:
> + * For uncompressed stream, data is valid for only half the active
> + * window, since the data rate is doubled in this mode.
> + * For compressed stream, data validity window needs to be adjusted for
> + * compression ratio and then further halved.
> */
> - if (p->wide_bus_en && !dp_intf)
> + if (p->compression_en && !dp_intf) {
> + if (p->wide_bus_en)
> + data_width = DIV_ROUND_UP(p->dce_bytes_per_line, 6);
> + else
> + data_width = DIV_ROUND_UP(p->dce_bytes_per_line, 3);
I was concerned about DPU < 5.0, but data_width is only used for
HCTL-related timings, which means DPU 5.0+. I'll look at restructuring
the code.
> + } else if (p->wide_bus_en && !dp_intf) {
> data_width = p->width >> 1;
> + }
>
> /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
> if (p->compression_en && !dp_intf &&
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index f6ef2c21b66d..badd26305fc9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -35,6 +35,7 @@ struct dpu_hw_intf_timing_params {
>
> bool wide_bus_en;
> bool compression_en;
> + u32 dce_bytes_per_line;
> };
>
> struct dpu_hw_intf_prog_fetch {
>
> ---
> base-commit: f338e77383789c0cae23ca3d48adcc5e9e137e3c
> change-id: 20260322-fix-data-width-calc-c44287df08b8
>
> Best regards,
> --
> Alexander Koskovich <[email protected]>
>
>
--
With best wishes
Dmitry
