On Fri, Mar 20, 2026 at 02:20:15PM +0100, Krzysztof Hałasa wrote: > Maxime Ripard <[email protected]> writes: > >>>>> - writel(FIELD_PREP(PANIC0_THRES_LOW_MASK, 1 * PANIC0_THRES_MAX / 3) | >>>>> - FIELD_PREP(PANIC0_THRES_HIGH_MASK, 2 * PANIC0_THRES_MAX / 3), >>>>> + writel(FIELD_PREP(PANIC0_THRES_LOW_MASK, DIV_ROUND_UP(1 * >>>>> PANIC0_THRES_MAX, 3)) | >>>>> + FIELD_PREP(PANIC0_THRES_HIGH_MASK, DIV_ROUND_UP(2 * >>>>> PANIC0_THRES_MAX, 3)), > >> If this is related to the output resolution, the DT is the last place >> you should deal with this. > > Well... just tested (v6.19 + patch) with 2160p30 and, surprise surprise, > it doesn't work for like 10% of the time. I.e., the display may freeze > at weston start and/or shutdown time, but otherwise works:
If you may use a display mode with low resolution, say 640x480p60, and the issue still happens, then I bet it's not related to the panic threshold settings, but more likely related to KMS detail control seqeunce. This reminds me that Lucas had a patch series[1] to try to fix the sequence, but it seems that it didn't fix i.MX93 LCDIF according to [2] hence no landing. [1] https://lore.kernel.org/all/[email protected]/#t [2] https://lore.kernel.org/all/am7pr04mb7046ff021b8ba46efb758ba098...@am7pr04mb7046.eurprd04.prod.outlook.com/ Cc'ing Lucas. > > v6.19 (frozen screen while starting weston, same display, the patch > applied): > 32FC6000: 2 2 2 2 > 32FC6010: 80000000 8700F00 12800B0 480008 > 32FC6020: A0058 1000007 0 > 32FC6030: 1 1 > 32FC6200: 8700F00 223C00 EF000000 > 32FC6210: 0 89000000 1 > 32FC6220: 0 0 0 0 > 32FC6230: 0 0 AB0155 > > OTOH NXP's 6.6.23 works all the time: > NCP v6.6.23 (a different i.MX8MP): > 32FC6000: A A A A > 32FC6010: 80000000 8700F00 12800B0 480008 > 32FC6020: A0058 10005 0 > 32FC6030: 1 1 > 32FC6200: 8700F00 A23C00 97C00000 > 32FC6210: 0 89000000 1 > 32FC6220: 0 0 0 0 > 32FC6230: 0 0 AB0155 A newer downstream kernel with newer kernel version dumps reg@32FC6230 as 0x01000180 instead of 0xAB0155. Note that this downstream kernel sets lcdif3 thresholds in DT: &lcdif3 { status = "okay"; thres-low = <1 2>; /* (FIFO * 1 / 2) */ thres-high = <3 4>; /* (FIFO * 3 / 4) */ }; I didn't tune/determine the threshold settings for downstream kernel, so what could I say? Maybe, align upstream kernel with downstream kernel. > > 32FC600x 2 vs. A is pixel clock inversion. > 32FC6208 is config P_SIZE, T_SIZE + pitch. > > More tests after weekend. -- Regards, Liu Ying
